IEEE Solid-States Circuits Magazine - Winter 2023 - 47

as a passive energy storage element
to improve these metrics and reduce
heat generated in the system battery
chargers, while providing bidirectional
operation. Some designs focus
on compute power delivery and
work to place a final power conversion
stage close to the load by using
a vertical power delivery concept. In
power delivery for computing applications,
the use of high switching frequencies
and meeting strict transient
requirements remain core objectives
and key challenges, respectively.
GaN designs are expanding in
scope and demonstrating higher
levels of integration for high-voltage
and automotive applications.
This year, we have seen an increase
in the complexity and feature set of
monolithic GaN designs with new
analog circuit concepts providing
functionalities that previously were
reserved for Si-only designs. There
are new concepts in gate driving
for GaN and SiC that achieve high
common-mode transient immunity
and provide adaptive switching
for improved performance as well
as spread spectrum techniques to
reduce EMI. Additional concepts
include gate drive signaling across
(up to 20 kV) galvanic isolation
barriers, which are also subject to
high delta voltage/delta time transients.
GaN-based power conversion
designs include high conversion ratio,
bidirectional buck-boost, and
flyback topologies.
Other areas of focus at ISSCC 2023
include wireless power transfer (WPT)
and energy harvesting. In particular,
energy harvesting techniques, such
as bias-flip piezoelectric, multisource
harvesting, and MPPT, are explored
in several papers. WPT papers
include techniques for foreign object
detection and methods to improve
the spatial distribution of EM
energy by using multipath transmitters.
Other concepts, such as new
receivers and rectifiers with adaptive
zero current switching and
hybrid techniques, some pushing
to very high operation frequencies,
are also explored.
Data Converters
Subcommittee Chair: Jan Westra,
Broadcom, Bunnik, The Netherlands
Data converters are a critical link
between the analog physical world
and the world of digital computing
and signal processing, prevalent
in modern electronics. The need to
faithfully preserve the signal across
domains continues to pressure data
converters to deliver more BW and
linearity while continuing to increase
power efficiency. This year, ISSCC not
only continues the trend of reporting
highly energy-efficient ADCs but also
showcases new and exciting converter
architectures, which opens new
possibilities for data conversion.
Time-based quantization and hybrid
pipelined-SAR architectures are
expanding the speed limits of the
current state of the art in Nyquist
converter design, while incremental
converters are reaching new levels of
efficiency. In noise-shaping converter
design, delta-sigma and noise-shaping
SAR converters are continuing
their prominent role and show their
strengths in both high-efficiency as
well as high-speed data conversion.
Various types of dynamic amplifiers,
such as ring amplifiers and floating
inverter amplifiers, are one of the key
aspects in pushing the limit of power
efficiency in these architectures.
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
1.E-01
10 20 30 40 50 60 70 80 90 100 110 120
SNDR at fin,hf (dB)
ISSCC 1997-2022
FOMW = 1 fJ/Conversion Step
FOMS = 185 dB
ISSCC 2023
FIGURE 2: The ADC power efficiency (P/fsnyq) as a function of the SNDR.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2023
47
Figures 2, 3, and 4 represent traditional
metrics that capture the innovative
progress in ADC design. Figure 2
plots power dissipated relative to the
Nyquist sampling rate (P/fsnyq), as a
function of SNDR, to give a measure
of ADC power efficiency. Note that a
lower P/fsnyq metric represents a more
efficient circuit on this chart. For lowto-medium-resolution
converters, energy
is primarily expended to quantize
the signal; thus, the overall efficiency
of this operation is typically measured
by the energy consumed per conversion
and quantization step. The dashed
trend line represents a benchmark of
1 fJ/conversion step. Circuit noise becomes
more significant with higherresolution
converters, necessitating a
different benchmark proportional to
the square of the SNR, represented by
the solid line. Designs published from
1997 to 2022 are shown in circles. ISSCC
2023 designs are shown in red stars.
Figure 3 plots signal fidelity versus
the Nyquist sampling rate normalized
to power consumption. At
low sampling rates, converters tend
to be limited by thermal and flicker
noises, independent of the sample
rate. Higher speeds of operation present
additional challenges in maintaining
accuracy in an energy-efficient
manner, indicated by the roll-off
versus frequency in the dashed line.
The past 10 years have resulted in an
P/fsnyq (pJ)
IEEE Solid-States Circuits Magazine - Winter 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2023
