IEEE Solid-States Circuits Magazine - Winter 2023 - 59
of DRAM will be explained, including
probabilistic aggressor tracking
against row hammer attacks and
core bias modulations to overcome
process limitations. Meanwhile, the
evolution of the memory high-speed
interface continues by using singleended
PAM-4 technology to achieve
1.E+3
speeds of 16 Gb/s/pin. NVM continues
to be applied to more advanced
process nodes and expand into a
wider range of applications. This
year, a 16-nm spin-transfer torque
(STT) MRAM that can operate in automotive
environments (an increased
temperature range) and a 22-nm nearmemory-computing
macro using STTMRAM
are presented. In addition, the
latest CIM developments are shown:
increased energy efficiency, throughput,
precision, and accuracy.
The top papers from ISSCC 2023
include:
■ " A 1.67Tb, 5b/Cell Flash Memory
Fabricated in 192-Layer Floating
Gate 3D NAND Technology and
Featuring 23.3Gb/mm2 Bit Density "
1.E+2
■ " A 16nm 32Mb Embedded STT-MRAM
with 6ns Read Access Time, 1M Cycles
Write Endurance, 20 Years Retention
at 150 ˚C and MTJ-OTP Solutions
for Magnetic Immunity "
1.E+1
■ " A 22nm 8Mb STT-MRAM NearMemory-Computing
Macro with 8bprecision
and 46.4-160.1TOPS/W for
AI-edge Devices "
1.E+0
■ " A 22-nm 832-kb Hybrid-Domain
Floating-Point SRAM In-Memory-Compute
Macro with 16.2-70.2TFLOPS/W
for High-Accuracy AI-Edge Devices "
1.E1
1.E+0 1.E+1 1.E+2 1.E+3
(2016-2020) 16 b
(2021) 4 b
(2023) 8 b
(2016-2020) 8 b
(2022) 8 b
(2023) 4 b
1.E+4 1.E+5 1.E+6
Throughput (GOPS)
(2016-2020) 4 b
(2022) 4 b
(2021) 8 b
(2023) 16 b
FIGURE 24: The deep learning processor energy efficiency (TOPS/watt) and throughput (GOPS).
1.E+04
16 b8 b4 b2 b Binary/Ternary
1.E+03
1.E+02
1.E+01
1.E+00
1.E01
(a)
1.E+01
1.E+00
1.E01
1.E02
1.E03
(b)
FIGURE 25: The (a) evolution in energy efficiency (TOPS/watt) and (b) throughput/unit area (TOPS/square millimeter) of ML inferencing processors.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2023
59
1.E+02
16 b8 b4 b2 b Binary/Ternary
■ " A 4nm 16Gb/s/pin Single-Ended
PAM4 Parallel Transceiver with
Switching Jitter Compensation and
Transmitter Optimization "
■ " CTLE-Ising: A 1440-Spin Continuous-Time
Latch-based Ising Machine
with One-Shot Fully-Parallel
Spin Updates Featuring Equalization
of Spin States "
■ " A 1.1V 16G DDR5 DRAM with Probabilistic
Aggressor Tracking, Refresh
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
Maximum TOPs/W at Emin
Energy Efficiency (TOPS/W)
Maximum TOPs/mm2 at VMAX
IEEE Solid-States Circuits Magazine - Winter 2023
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2023
Contents
IEEE Solid-States Circuits Magazine - Winter 2023 - Cover1
IEEE Solid-States Circuits Magazine - Winter 2023 - Cover2
IEEE Solid-States Circuits Magazine - Winter 2023 - Contents
IEEE Solid-States Circuits Magazine - Winter 2023 - 2
IEEE Solid-States Circuits Magazine - Winter 2023 - 3
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IEEE Solid-States Circuits Magazine - Winter 2023 - 58
IEEE Solid-States Circuits Magazine - Winter 2023 - 59
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IEEE Solid-States Circuits Magazine - Winter 2023 - 104
IEEE Solid-States Circuits Magazine - Winter 2023 - Cover3
IEEE Solid-States Circuits Magazine - Winter 2023 - Cover4
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