IEEE Solid-States Circuits Magazine - Winter 2023 - 69

(LNA) output node can be tuned by
changing the digitally controlled ca -
pacitance to ensure center frequency
alignment with subsequent stages.
This additional capacitance will ultimately
reduce the bandwidth of this
LNA but allows a usable output even
when the parasitic capacitance varies
by up to ±20%.
The RISC-V µProcessor
The design includes a fully custom-made
dual-issue 64-bit microprocessor
named RISu064. It's an
achievement made possible by the
RISC-V community. For many years,
the RISC-V community has dedicated
itself to demystifying the implementation
of modern processors. On
GitHub, hundreds of implementations
comply with the RISC-V instruction
set architecture, ranging from small
cores like PicoRV32 to enormous
ones like the Berkeley Out-of-Order
Machine (BOOM). The source code is
a goldmine for motivated learners.
Figure 7 shows the partitioning of the
microprocessor layout.
Mixer
Low Noise
Amplifier
Digitally
Controlled
Oscillator
Digitally
Controlled
Oscillator
Power
Amplifier
The Open Source Workflow
and Toolchain
The open source tools grant the user
complete control of the flow, while
proprietary software is well established
and fully featured. Still, users
often need to ask the supporting personnel
from their companies to be
able to use those features effectively.
The open source world is a different
story. We get the highest flexibility
in the sense that we can customize
every single step of the flow and
tailor it to fit our needs, but it also
demands that the user gain a deep
understanding of every step, which
makes it an excellent tool for education.
Figure 8 shows the complete
open source flow the team used to
implement the design.
As shown in Figure 8, compared
FIGURE 4: A transceiver layout with highlighted blocks. Preamp.: preamplifier.
3.3 V
to the commonly used XSchem and
MAGIC tools [3], extra steps have
been introduced for the RF/analog
flow, such as the simulation of
the planar inductor with the Berkeley
ASITIC [4] and Massachusetts
Institute of Technology FastHenry2
[5] tools. The inductor layout was
done using a GDSPY-based inductor
generator, namely the Maelhos
Matching
Bias
Preamp.
Matching
Stabilizer
Bias
1 V
Digitally
Tuned
Capacitor
Matching
FIGURE 5: A class-E PA schematic versus layout.
FIGURE 6: An LNA schematic with digital
calibration.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2023
69
Preamp.

IEEE Solid-States Circuits Magazine - Winter 2023

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2023

Contents
IEEE Solid-States Circuits Magazine - Winter 2023 - Cover1
IEEE Solid-States Circuits Magazine - Winter 2023 - Cover2
IEEE Solid-States Circuits Magazine - Winter 2023 - Contents
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IEEE Solid-States Circuits Magazine - Winter 2023 - Cover3
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