IEEE Solid-States Circuits Magazine - Winter 2023 - 9

VDD
VDD
RD
X
M2
P
M1
Iin
Cin
RF
(a)
Iin
Cin
Vout
RF
RD2
(b)
Rin
P
M1
+
V1
-
−AV1
+ RD2
-
(c)
FIGURE 8: (a) A feedback TIA using a PMOS follower; (b) the circuit of (a) with a CG stage added; and (c) a circuit model for computing the
input resistance.
Illustrated in Figure 6, the issue is
that the data experiences a " droop "
during long runs, possibly precluding
proper detection. For this reason,
the interfaces in such receivers
must typically rely on dc coupling,
a condition that makes low-voltage
design challenging.
For example, consider the feedback
realization in Figure 7, which
incorporates a source follower to
drive
R .F We have VV .V=+ GS
X 21GS
Resistor RD can therefore sustain a
dc drop of only (),VV V21DD
-+ GS
GS
limiting the voltage gain of the common-source
(CS) stage. If node X is
capacitively coupled to the gate of
M ,2
this issue is resolved, but the
droop manifests itself.
TIA Topology
We wish to replace the source follower
in Figure 7 with a circuit that does
not create a large positive or negative
level shift. For the CS stage to provide
a reasonable voltage gain, the dc drop
across RD
value for VX
imposes a relatively low
(equal to the overdrive
voltage of M ).1 We then surmise that
this node must be sensed by the gate
of a PMOS device. Depicted in Figure
8(a) is one possibility, where the
PMOS source follower M2
introduces
a positive level shift. It appears that
Vout
hence, -=;; Since V 2GS
is typically greater than V ,1TH
inevitably resides in the triode region.
VV .V11 GS2
GS
VV ,V12 1
DS
DS ;; GS
GS
;;
M1
Iin
is now compatible with the gate
of M ,1 but a closer look reveals otherwise.
We have += and
Cin
Rin
W
L
=
10 µm
30 nm
FIGURE 9: The preliminary TIA implementation.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2023
9
RD1
P
M1
1 kΩ
X
M2
1 kΩ
Vout
RF
RD2
1 kΩ
ISS
This calculation suggests that the RR .D2 Using the model shown
voltage at the source of M2
out
must
be shifted down before reaching the
gate of
M .1 This can be accomplished
by a CG stage, as illustrated in Figure
8(b). We can also view M2
M3 as a differential pair, expecting
some voltage gain from X to V .out
Let us examine the circuit's bias
conditions. With a high loop gain,
VX
V ,b
adjusts itself to remain around
defining ID1
as ()/.VV RbD1
DD
-
According to this current, M1 develops
a certainV ,GS which also appears at the
drain of M .3 That is, ;;= GS
II .IDD
31 2
and ;; SS ;;=- To maximize the
23
therefore, selectRV /( /).
We should remark that the expressionRR
)A1F
II /,I 2DD
=
D21GS
/(
topology of Figure 5 tacitly assumes
a zero-output impedance for the core
amplifier. In Figure 8(b), on the other
hand, the open-loop circuit exhibits
voltage gain of the differential pair,
we must have
and
.
in Figure 8(c), we have
R
in =
RR
1
FD2
+
+ A
(10)
where A denotes the unloaded openloop
gain.
The Preliminary Design
We begin with the design shown in
Figure 9, where the sources of M2
M3 are tied to their n-well so as to
and
avoid the rise in their threshold voltage
due to the body effect. Since Vb
=
IV /RDD 300mV we have ()/IV VR
09 .)/.k5031 065VV
DD
(. -=X
23 SS.. and
ISS 2
in=+ obtained for the
, ..mA.
The
Db D11
CS stage and the differential pair display
voltage gains equal to 3.5 and
1.1, respectively, offering a loop gain
of 3.9.
How do we select the value of
R ?F We surmise from (9) that the
term /kT R4
F $
R 200X for
I in = 10pA Hz
n,
2
But such a low transimpedance gain
VDD = 0.95 V
1 mA
Vb = 300 mV
M3
VDD
30 nm
5 µm
F is dominant, dictating
/.
Vout
RD1
X
M2 M3
ISS
Vb
RF
IEEE Solid-States Circuits Magazine - Winter 2023

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