IEEE Power Electronics Magazine Compendium - March 2018 - 46

faces between each surface and the ambient world. This
drain, and source are all on one surface-compared with
leads to four key variables: 1) thermal resistance from the
most power MOSFETs, which are vertical devices, i.e., the
device to the PCB ^ R iJB h, 2) thermal resistance from the
gate and source are on one surface of the device, and the
drain is on the opposite surface. Figure 2 shows various
PCB to the outside ambient ^ R iBA h, 3) thermal resistance
chip scale formats for commercially available eGaN FETs.
from the junction to the back of the device, or case ^ R iJC h,
Unlike low-voltage lateral MOSFETs that become uncomand 4) the thermal resistance from the back of the device
petitive around 30-40 V when compared with the more
to the outside ambient ^ R iCA h . Only the R iJB and R iJC are
common vertical silicon MOSFETs, eGaN FETs are capauniquely controlled by the package. The other components
ble of exceeding vertical MOSFET performance to 300 V
of thermal resistance are controlled by user-controlled variand beyond.
ables, such as heat sinks, thermal interface materials, and
Figure 1 also shows the switching losses related to the
the choice of copper thicknesses in the PCB layout, among
chip-scale format. Only 18% power loss is added to the
others. Figure 3(a) shows the relationship between the trandevice due to the minimal inductance of a packageless
sistor footprint and R iJB . As the footprint gets smaller, the
package. For reference, the different eGaN FET chip-scale
thermal resistance increases in a smooth function indepenpackages available and their related
dent of technology. Figure 3(b) shows
generations [2], [4], [5] are shown to
relationship between R iJC and the
scale in Figure 2.
package area. The chip-scale packSemiconductor
At this point, we have shown that
age has a distinct advantage in perforGaN technology is producing transismance. This is due to the lack of any
packaging adds a
tors that have lower on-resistance,
interface between the back surface
significant amount of
of the GaN transistor and the outside
have faster switching, and are smaller.
world. Silicon devices need an interThe size advantage comes from a
inductance to the
vening layer of interface material to
smaller device area due to the effisystem and can,
shuttle the drain current from the
ciency of the GaN crystal and the lack
back surface to the PCB. This extra
of a surrounding package. However,
therefore, attenuate
layer impedes the flow of heat.
as many power system designers have
performance.
Thus, for systems where the domiexperienced, smaller is not always betnant thermal path is down through
ter. As a system gets smaller, there is
the PCB, the overall thermal pera greater challenge to getting the heat
formance of the smaller eGaN FETs will be better as
out. Now, we will look at the basic thermal performance of
the thermal resistance of the PCB will dominate (there
eGaN transistors in chip-scale packages.
is only about 1 cC/W variation in R iJB between the largest and smallest devices presented), while the equivalent
Thermal Conductivity
losses will decrease. Furthermore, as the power density
We have already shown that commercially available
and, therefore, power loss density of converters continue
eGaN transistors are more efficient than their aging silito increase, the need for dual-sided cooling means than
con counterparts. This improved efficiency implies that
a much lower thermal resistance from the case to ambithere is less heat generated in the device. However, since
ent can be achieved through the top of the device, and
the GaN transistors are also much smaller, it is important
improvements here will have a larger impact on thermal
to examine how efficiently the heat generated within the
performance.
device can be removed.
Switching speed, on-resistance, thermal performance,
Heat can be extracted from a device from both the front
surface and the back surface. There are at least two interand size-GaN transistors are superior to silicon MOSFETs

2.3 mm
Solder-Side View
Solder-Sid
6 mm

Generation 2
fig 2 The chip-scale packages for eGaN FETs.

IEEE PowEr ElEctronIcs MagazInE

z March 2015

Generation 3

Generation 4

Half-Bridge

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine Compendium - March 2018