IEEE Power Electronics Magazine Compendium - March 2018 - 47

Power transistor manufacturing costs have five basic components: 1) substrate costs, 2) the cost to grow the epitaxial
crystal layer on top of the substrate, 3) the cost to process
the product in a wafer fabrication facility, 4) the cost of testing, and 5) the cost of packaging. There have been publications that explain these steps in much greater detail [1], and
it is the sum of these five elements that determine the cost of
a final transistor. Breaking the manufacturing costs down
this way illustrates where the cost challenges are and where
they are going.
A comparison of silicon MOSFETs and their GaN
counterparts with the same rated voltage and on-resistance is shown in Figure 4. This comparison ignores
the relative advantages GaN transistors have in every
other aspect of performance and value. The comparison can be different for different die sizes. For example,
in a silicon MOSFET finished product, the average cost
of packaging is half the total product cost. Smaller die
sizes have an even larger percentage of cost represented in the package. Figure 4(a) shows the cost comparison for GaN transistors with device area under
3 mm2. It shows the costs in 2014 and the expected costs
by the end of 2016. The starting material costs are lower
for the GaN transistors due to the smaller size of the
chip for the same on-resistance and voltage. The cost of
growing the GaN heterostructure, however, is higher due
to the relatively low level of equipment utilization. This
cost differential is compensated by the relatively higher
number of good devices per wafer. Wafer fabrication
takes place in a standard trailing-edge silicon foundry,
and GaN wafers run side-by-side silicon complimentary metal-oxide semiconductor integrated circuits and
trench power MOSFETs. The eGaN transistors, however,
have far fewer steps than their MOSFET cousins, but the
volumes are much lower. As a consequence, today the
fabrication costs are similar, but, as volume grows, pric-

2014

3
RiJB, Thermal Resistance
(°C/W)

Cost

ing leverage will turn the advantage toward GaN. Testing
costs will always be similar for similar functions, and the
total elimination of the package yields an immediate-
and large-relative advantage to the GaN devices.
Figure 4(b) is the comparison for GaN transistors with
a device area greater than 7 mm2. Today, due to higher
yields, the smaller dies are already lower cost to produce
than equivalently rated but much lower performance power

RiJB_Si
RiJB_GaN

2.5
2
1.5
1
0.5
0

10
15
20
25
Device Area (mm2)
(a)

3
RiJC, Thermal Resistance
(°C/W)

on all counts. That leaves cost, and we examine how the
manufacturing cost of GaN transistors compares to silicon
in the next section.

RiJC_Si
RiJC_GaN

2.5
2
1.5
1
0.5
0

10
15
20
25
Device Area (mm2)
(b)

fig 3 The thermal conductivity comparison between eGaN FETs
and power MOSFETs in a variety of popular packages: (a) the
relationship between package area and thermal resistance from
the device to the PCB ^R iJB h and (b) the thermal resistance from
the junction to the back of the device, or case ^R iJC h .

2016

2014

2016

Starting Material

Lower

Starting Material

Lower

Epi Growth

~Same

Lower

Epi Growth

Higher

~Same

Wafer Fab

Same

Lower

Wafer Fab

Same

Lower

Test

Same

Test

Same

Assembly

Lower

Assembly

Lower

Overall

Lower

Overall

Higher

Lower

(a)

(b)

fig 4 A comparison of product costs between an equivalently rated GaN transistor and silicon MOSFET: (a) die sizes fewer than
3 mm2 and (b) die sizes greater than 7 mm2.

March 2015

z IEEE PowEr ElEctronIcs MagazInE

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine Compendium - March 2018