IEEE Power Electronics Magazine Compendium - March 2018 - 82

gate driver. This required in-house development of the gate
driver, with a parasitic interwinding coupling capacitance of
3.4 pF at 50 MHz to handle such high dv/dt stress. The
11-kV, high- dv/dt gate driver prototype is shown in Figure 5.
The validation of the gate driver in HV, hard-switched, HF,
high- dv/dt test circuits is another critical element. The gate
driver was evaluated on boost-fed-buck converter and buckboost converter topologies to expose the gate driver to highside voltage and dv/dt (over 100 kV/ns at 11-kV dc) as well as
voltage swings from -2 to +8 kV [15]. In addition, the electromagnetic interference (EMI) robustness was validated by
probing several signals and Vcc of different ICs on the gate
driver power supply [15].

Modular 3L-NPC Converter for TIPS
fig 5 The HV isolated gate driver prototype for the 15-kV
SiC IGBT [15].

has a much faster transition. A detailed analysis of dv/dt of
both the 15-kV SiC IGBTs is presented in [13].

MV Gate Driver
Commercially available gate driver isolation power supplies
have a maximum dielectric test voltage (50 Hz, 1 minute) of
18-kV root mean square (rms) [14]. These power supplies
are meant for application in 6.5-kV Si IGBT-based multilevel
converters, where the dv/dt values and switching frequencies are expected to be at least an order of magnitude lower
than that of the 15-kV SiC IGBTs. The 15-kV SiC IGBTs present a completely different scenario, with dv/dt greater than
100 kV/ns and with an operating dc voltage up to 11 kV as
well as a high switching frequency (5-10 kHz), which will
require significant derating for the reliable operation of the

Gate Driver
Power Supply
Board with
HV Isolation

Based on the switching loss measurements, the hardswitching frequency limits of the 15-kV SiC IGBT were evaluated and demonstrated on a 10-kV dc-dc boost converter
[10]. It was found that the high thermal resistance of the
module package is pivotal in determining the SiC IGBT
thermal limits. The thermal resistance was found to be
0.49 °C/W from the junction to the top of the heat sink. The
3L-NPC converter design and demonstration results with
10-kV dc input are presented in [16].
The 3L-NPC converters on the MV side of the TIPS
have a modular structure with three poles for the AFEC
stage and three poles for primary side of the DABC. Each
3L-NPC pole has its own dc-link capacitor with a bus-bar
connection to the 15-kV SiC IGBTs and 20-kV (2 # 10 kV)
SiC JBS clamping diodes for low stray inductance. The
poles were individually tested up to 10-kV dc input
in inverter mode at 5 kHz and 7.5 kW before integrating them into the three-phase TIPS. Figure 6 shows a
3L-NPC pole mounted on HV bushings for reducing common-mode currents. The PWM signals are transmitted
optically to minimize EMI
issues and provide higher
voltage isolation as well as
controller operation distant
Bleeder
Resistor
from the TIPS 3L-NPC converter poles.
Three-Level
Pole Bus
Bar

Gate Driver
Board

dc Bus
Capacitors

20-kV SiC
JBS Clamping
Diode

Heat-Sink
Choke

15-kV SiC
IGBT
Outlet Fan Set

Heat Sink

Porcelain
Insulation

fig 6 A pole of a 3L-NPC converter [31].

IEEE PowEr ElEctronIcs MagazInE

z September 2015

Fiberglass
Insulation

Active Front-End
Converter
The AFEC is a critical stage of
the SST. It handles many functions, including unity-powerfactor (UPF) operation,
power-factor control, regulating the MV dc bus, grid-side
power-quality improvement,
and var compensation. With
higher switching frequencies
of 3-10 kHz possible with HV
10-15-kV SiC devices, the filter
inductance can be as low as

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine Compendium - March 2018