IEEE Power Electronics Magazine - December 2015 - 51

Efficiency (%)

Power MOSFETs, capacitors, and inductors are
97
all commercial off-the-shelf (COTS) pedigree and
96
were procured from commercial vendors. All parts
95
are surface-mount devices and compatible with
94
automatic pick-and-place machines. MOSFETs
93
4 Vin_model
were selected based on the best parts available and
5 Vin_lab
92
application-specific optimization. Capacitors were
5 Vin_model
91
selected based on availability and long-term reli4 Vin_lab
90
6 Vin_model
ability data from vendors. Planar magnetics were
89
6 Vin_lab
used to lower the profile and distribute the mass.
88
8 Vin_model
An application-specific integrated circuit (ASIC)
87
8 Vin_lab
was developed. The ASIC die is shown in Figure
86
4(c). The ASIC is fabricated with a technology node
85
84
of 180-nm power CMOS. There are a few unique fea0
1
2
3
4
5
6
7
8
9
10
tures built in the ASIC. It has two independently reguIout (A)
lated outputs developed for meeting typical APOL
insertion needs. To minimize the input ripple, the
FIG 5 The consistent agreement between the loss analysis prediction and
two channels were phase-staggered by 180°. Current
the measured data validates the model.
programming is used to maximize dynamic perforFigure 6 shows one typical case of the prediction of varimance and improve load-sharing capability. Both the
ous losses in the converter design. For the 98.59% efficient
synchronization and current sharing can be implemented with
design, the top-tier losses are: high-side FET conduction
a single-wire connection. The ASIC is an ultra-efficient design,
loss (hs cond, 0.33%), low-side FET conduction loss (ls cond,
consuming about 300 mW when driving full load.
0.13%), inductor dc resistance loss (ind dcr, 0.18%), PWB dc
The efficiency performance target was selected for the
resistance loss (Rpbc, 0.155%), high-side FET switching loss
APOL to achieve 98.5% overall power efficiency. The de(hs sw, 0.11%), high-side FET drive loss (hs drv, 0.11%), lowsign was also set to be capable of operating efficiently from
side FET drive loss (ls drv, 0.10%), and body diode loss (bdy
0.8 to 3.3 V at input, with an output current capability of 9 A
diode, 0.11%).
and the maximum efficiency at about 3-A load current.
Device and control IC specifications were also guided
A detailed loss analysis and optimization tool for the speby this design-specific optimization tool. Note that, in the
cific design was developed in Microsoft Excel. It includes
optimized design, the high-side FET conduction loss and
detailed analysis for every single part of the converter. Its
inductor resistance (conduction) loss are still larger than
usefulness was first validated by test data and then applied
others, indicating this is a conduction loss limited design,
for optimization. Refer to Figure 5, where the predictions
as it should be for any high-density designs. It also points
and measured results are plotted together. Consistent
to the limits that state-of-the-art components placed on
agreement between the predicted and measured efficiency
that design at the time (hence are opportunities for furcurves over the line and the load validates the accuracy and
ther improvement).
effectiveness of the model.
ind core 0.01%
ls cond 0.13%
pout 98.59%

hs cond 0.33%

ind dcr 0.18%
pqssh 0.02%
pqssl 0.02%
psnb 0.03%
pbstp 0.00%

Other 1.41%

bdy diode 0.11%
Rpbc 0.15%
bias 0.10%
hs sw 0.11%
hs drv 0.11%

ls drv 0.10%

FIG 6 The loss analysis for the APOL prototype, predicting an achievable efficiency of 98.59%.

December 2015

z IEEE PowEr ElEctronIcs MagazInE

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - December 2015