IEEE Power Electronics Magazine - December 2015 - 52

Note that a general design-optimization tool may not be
as effective as a design-specific optimization tool to achieve
the best efficiency, since the loss distribution is a strong
function of design parameters such as output voltage, current, layout, thermal design, and size constraints. Also note
that application-specific optimization also allows the bus
converter design and bus voltage selection to be leveraged
directly as design parameters to maximize the efficiency
for individual power stage and the overall power distribution system. This is a significant advantage of the adiabatic
power-conversion technology and the double-regulated intermediate bus [10]-[13].

Measured Results
Once the APOL prototype was built and brought up to full
operation with tight regulation and fast dynamic performance, extensive efficiency data were collected over the
line, the load, and the temperature. Figure 7 shows a family
of curves for measured efficiency data. The seven curves
were taken from a typical application temperature range of

Efficiency (%)

98.50
98
97.50

Temp = -30 °C
Temp = -20.0 °C
Temp = -9.5 °C
Temp = 0.1 °C
Temp = 25.6 °C
Temp = 45.6 °C
Temp = 65.4 °C

97
96.50
96

Iout (A)
FIG 7 The measured APOL efficiency, demonstrating a record
99% at 4 Vin, 3.3 Vout, and 3 A.

-30 to 65 °C in increments of about 10 °C. The best efficiency was measured to be 99% for the design with 4 Vin and
3.3 Vout at about 3-A output load current. Over the target
nominal operating load current of 2-3 A, the efficiency
stays above 98.75% for all the temperatures. Over the entire
temperature and load ranges, the efficiency was measured
between 97.5% and 99%. The general shape of the curves
indicates that this is conduction loss limited design as we
observed before. The measured efficiency results far
exceeded our targeted performance of 98.5%. The board
was then further tested to a 60-W total power, twice the
designed capability. The performance was maintained
throughout the load range without undue degradation.
To enhance APOL's manufacturability and testability for high-rate production, the number of potential dash
numbers needed for production for each payload ship set
should be reduced. To this end, a converter design with the
capability for user-settable voltage levels were implemented and tested to meet the specification.
Figure 8 presents the measured efficiency numbers with
different output voltage levels ranging from 0.8 to 3.3 V. The
best efficiency for 0.8-V output is about 95.9%, and the efficiency at a full load current of 9 A is above 92.5%. Note that
no special efforts were made to optimize the design for low
voltage levels, since it can be pursued later by utilizing the
same design specific optimization approach for prescribed
efficiency at a given output level.
For benchmarking purposes, the APOL, when driven
by a bus converter module (BCM), was measured and
compared with a well-known COTS chipset on the market.
Figure 9 shows the measured efficiency curves for two
sets of power converters. The top family is for the case
where the APOL prototype was driven by a BCM prototype
(for more details, see [13] and [14]), and the bottom family
of curves is for the case where the COTS chipset was used.
It can be clearly observed in Figure 9 that the APOL design outperformed the COTS hardware consistently over

Efficiency (%)

99
98

Freq = 150 kHz, Vinp = 4 V, Vin5 = 4.8 V,
Vout = 3.3 V, Iout = Variable

Freq = 150 kHz, Vinp = 4 V, Vin5 = 4.8 V,
Vout = 2.5 V, Iout = Variable

Freq = 150 kHz, Vinp = 4 V, Vin5 = 4.8 V,
Vout = 1.8 V, Iout = Variable

95
94

Freq = 150 kHz, Vinp = 4 V, Vin5 = 4.8 V,
Vout = 1.0 V, Iout = Variable

Freq = 150 kHz, Vinp = 4 V, Vin5 = 4.8 V,
Vout = 0.8 V, Iout = Variable

Iout (A)
FIG 8 The measured APOL efficiency, demonstrating robust efficient operation from 0.8- to 3.3-V output.

IEEE PowEr ElEctronIcs MagazInE

z December 2015

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - December 2015