IEEE Power Electronics Magazine - December 2020 - 30

1012

108
106

104

°C

0°

b
102 MTTF = A exp (-β V)exp a
kT
β = -9.2/V
7.5

8.5
9
Gate Bias (V)
(a)

1015
1010

10 Years
10

0
10 ppm
1 ppm
pp
m

105

100

100
9.5

25 °C

10 Years
Time to Failure (s)

Mean Time to Failure (s)

MAX Rating = 6 V

1020

1010

7
8
Gate Bias (V)
(b)

FIG 2 The (a) mean time to failure (MTTF) for EPC2212 eGaN FETs vs. VGS at both 25 °C and 120 °C. The (b) graph that shows the various probabilities of failure vs. VGS at 25 °C.

(EPC). The plot on the left has different voltages at room
temperature and the plot of the right shows two different
voltages applied at 120 °C. Note that this device has a data
sheet maximum gate voltage rating of 6 V, yet very few
devices are failing even after many hours at 8 V.
In Figure 2, these data have been translated into failure
rates. Looking at the graph on the right, with a VGS of 6 V
DC one could expect between 10 and 100 parts per million
(ppm) failures in 10 years. The recommended gate drive
voltage, however, is 5.25 V and the expected failure rate at
that voltage is less than 1 ppm in 10 years.
These conclusions are only valid if the primary failure
mechanism is the same under all these conditions. To confirm this, failure analysis was performed and a uniform
result was found, as shown in Figure 3 where the yellow
circle shows that the failure site is between the gate metal
and the metal 1 field plate layer.

Failures Site Between
Gate Metal and Metal 1
Field Plate

Metal 1
Dielectric

Gate Metal
GaN

FIG 3 Scanning electron micrograph (SEM) of the gate region
of an EPC2212 eGaN FET. Yellow circle shows the failure site is
between the gate metal and the metal 1 layer.

IEEE POWER ELECTRONICS MAGAZINE

z December 2020

In the case of the EPC2212, the gate metal and the
metal 1 field plate layer are separated by a silicon nitride
layer. It is this silicon nitride layer that failed, not any of
the GaN layers beneath. Knowing this failure mechanism
and understanding that it is consistent with time-dependent dielectric breakdown (TDDB) failure mechanisms
and impact ionization [5] commonly found in dielectric
layers, the probability data in Figure 2 to predict failure
rates due to gate-source stress within data sheet limits
can be used with confidence.

Drain-Source Voltage Stress
This same methodology can be applied to every other
stress condition. For example, one common concern
among GaN transistor users is dynamic on-resistance
(RDS(on)). This is a condition whereby the RDS(on) of a transistor increases when the device is exposed to high drainsource voltage (VDS). The traditional way to test for this
condition is to apply maximum-rated dc VDS at maximum
rated temperature (typically 150 °C). If there are no failures
after a certain amount of time - usually 1000 hours - the
product is considered good.
The mechanism causing the RDS(on) to increase is the
trapping of electrons. Once an electron is trapped, it can
no longer conduct and the resistance of the part increases.
By applying dc VDS at maximum temperature, the electrons
available to be trapped come from the drain-source leakage
current, IDSS, which is typically in the micro-ampere range.
In order to accelerate trapping, devices can be taken to voltages above their rated maximum, as shown in Figure 4 for a
100 V-rated EPC2212 eGaN FET.
In Figure 4 these data have been translated into time-tofail graphs versus voltage and temperature. On the right side
of the graph is shown the time for 1 ppm failures (0.0001%),

IEEE Power Electronics Magazine - December 2020

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