IEEE Power Electronics Magazine - December 2020 - 31

MTTF Versus VDS and Temperature

Time to Failure Versus VDS (150 °C)

10100

1025

90 °C
1080

Time to Failure TTF (s)

Mean Time to Failure MTTF (s)

1030

150 °C

1060
35 °C
1040
1020

1015

0.0001%

1010

20 Year Line

105

10 Year Line

100
80

0.01%
1020

100

110

120

130

140

100
80

EPC2212
90

100

110

120

Drain Voltage (VDS)

(a)

(b)

130

140

FIG 4 Data on device failures over time taken at different voltages and temperatures is statistically translated into predictions of
failure rates over time, temperature, and voltage.

100 ppm (0.01%), and 10,000 ppM (1%) at various VDSS. At this
device's maximum rated VDS of 100 V, the 1 ppm failure rate
is well above the 10-year line. What is unusual is that the
graph on the left shows that the failure rates are not very
sensitive to temperature and that the failure rates, although
extraordinarily low under all conditions, are even lower at
90 °C than at either 35 °C or 150 °C. This strange temperature
dependence can be explained by the fact that hot electrons
travel shorter distances at higher temperatures which offsets the increasing leakage current. These two competing
phenomena result in a lowest time-to-fail at about 90 °C.
Figure 5 is a magnified image of an EPC2212 eGaN FET
showing thermal emissions in the 1-2 µm optical range.
Emissions in this part of the spectrum are consistent with
hot electrons and their location in the device is consistent
with the location of the highest electric fields when the
device is under drain-source bias.
Knowing that hot electrons in this region of the device
are the source of trapped electrons, a better understanding of how to minimize the dynamic on-resistance can
be achieved with improved designs and processes. By
understanding the general behavior of hot electrons,
their behavior over a wider range of stress conditions
can be generalized.
In addition, the trapping mechanism can be accelerated
by providing more hot electrons. To do this, a circuit that
pushes high IDSS through the device at maximum rated VDS
was created. In other words, instead of just using the leakage current generated by dc bias at high temperatures as
the source of electrons that can get trapped, orders of magnitude more trapping candidates can be generated. The circuit used is like the inductive double-pulse testing specified
by JEDEC JEP173 [6].

Figure 6 shows how the RDS(on) of a 100 V EPC2045 eGaN
FET [5] increases over time at various voltage stress levels
and temperatures. The graph on the right of Figure 6 shows
the evolution of RDS(on) when biased at 120 V at different
temperatures. The counter-intuitive result shows that the
on-resistance increases faster at lower temperatures. This
is consistent with hot carrier injection because hot electrons travel further at lower temperatures and, therefore,
can get to different layers where they are more prone to
become trapped [7]. This suggests that traditional testing
methods, whereby a device is tested at maximum voltage
and temperature, may not be the best way to determine the
reliability of a device.
The results in Figure 4 can now be better understood.
As the device is heated under dc bias, the leakage current
increases. The shorter travel distance of the hot carriers,

FIG 5 Magnified image of an EPC2212 eGaN FET showing thermal emissions in the 1-2 µm optical range, consistent with hot
electron emissions near the drain edge of the transistor.

December 2020

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IEEE Power Electronics Magazine - December 2020

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