IEEE Power Electronics Magazine - December 2020 - 32

2

EPC2045
100 kHz

1.8

1

60 V 80 V 100 V

0.8

1,000 h

0.4
0.2 RDS(on) (t ) = α + βlog(t)
102

103

104
Time (min)
(a)

105

10 Year

0.6

106

25 °C

1.4

75 °C
125 °C

1.2
1
0.8
0.6
0.4
0.2
0
101

102

103

104
Time (min)
(b)

105

10 Year

Normalized RDS(on)

1.2

0
101

EPC2045
120 V, 100 kHz

1.6
120 V

1.4

2,500 h

Normalized RDS(on)

1.6

RDS(on) Shift Versus Temperature

2,500 h

1.8

RDS(on) Shift Versus Time and VIN (25 °C)

1,000 h

2

106

FIG 6 RDS(on) of an EPC2045 [8] eGaN FET over time at various voltage stress levels and temperatures. The (a) devices were tested at
25 °C at voltages from 60 V to 120 V. The (b) graph shows evolution of RDS(on) at 120 V at various temperatures.

ID-Drain Current (A)

EPC2034C 200 V
100

10
Limited by RDS(on)
1

0.1
0.1

1
10
100
VDS-Drain-Source Voltage (V)
100 µs Pulse (Pass)
100 µs Pulse (Fail)
1 ms Pulse (Pass)
1 ms Pulse (Fail)

FIG 7 EPC2034C SOA plot. " Limited by RDS(on) " line is based on
data sheet maximum specification for RDS(on) at 150 °C. Measurements for 1 ms (purple triangles) and 100 µs (green dots)
pulses are shown. Failures are denoted by red triangles (1 ms)
or red dots (100 µs).

however, counters this increase in available electrons such
that the RDS(on) does not increase over time as rapidly
from room temperature to 90 °C, but then starts increasing at higher temperatures as more carriers are available
- another counter-intuitive result.

Safe Operating Area
Safe operating area (SOA) testing exposes the eGaN FET
to simultaneous high current (ID) and high voltage (VDS)
for a specified pulse duration. The primary purpose is to

32	

IEEE POWER ELECTRONICS MAGAZINE	

z	December 2020

verify the FET can be operated without failure at every
point (ID, VDS) within the data sheet SOA graph. It can also
be used to probe the safety margins by testing to fail outside
the safe zone.
During SOA tests, the high-power dissipation within
the die leads to a rapid rise in junction temperature and
the formation of strong thermal gradients. For sufficiently high power and/or pulse duration, the device simply overheats and fails catastrophically. This is known as
thermal overload failure. In Si MOSFETs, another failure
mechanism known as secondary breakdown (or Spirito
effect [9]), has been observed in SOA testing. This failure
mode, which occurs at high VD and low ID, is caused by
an unstable feedback between junction temperature and
threshold VTH.
For dc, or long-duration pulses, the SOA capability of the
FET is highly dependent on the heat sinking of the device.
This can present a huge technical challenge to assess the
true SOA capability, often requiring specialty water-cooled
heatsinks. However, for short pulses (< 1 ms), the heat sinking does not impact SOA performance. This is because on
short timescales, the heat generated in the junction does
not have sufficient time to diffuse to any external heatsink.
Instead, all the electrical power is converted into raising
the temperature of the GaN film and nearby silicon substrate. In consideration of this, SOA tests were conducted
at two pulse durations: 1 ms and 100 µs.
Figure 7 shows the SOA data of a 200 V EPC2034C [10].
In this plot, individual pulse tests are represented by points
in (ID, VDS) space. These points are overlaid on the data
sheet SOA graph. Data for both 100 µs and 1 ms pulses data
are shown together. A broad area of the SOA was interrogated without any failures (all green dots), ranging from
low VDS all the way to VDS; max (200 V). All failures (red dots)
occurred outside the SOA, indicated by the green line in
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