IEEE Power Electronics Magazine - December 2020 - 33

Short Circuit Testing
Short-circuit robustness refers to the ability of a FET to
withstand unintentional fault conditions that may occur in a
power converter while in the ON (conducting) state. In such
an event, the part will experience the full bus voltage combined with a current that is limited only by the inherent
saturation current of the transistor itself and the circuit parasitic resistance. If the short-circuit state is not quenched by
protection circuitry, the extreme power dissipation will ultimately lead to thermal failure of the FET.
The goal of short-circuit testing is to quantify the withstand time the part can survive under these conditions.
Typical protection circuits (e.g. de-saturation protection
for IGBT gate drivers) can detect and react to over-current
conditions in 2-3 μs. It is therefore desirable for eGaN FETs
to withstand unclamped short-circuit conditions for about
5 μs or longer.
The two main test circuits used for short-circuit robustness evaluation are [11]:
■■Hard-switched fault (HSF): Gate is switched ON (and
OFF) with drain voltage applied
■■Fault under load (FUL): Drain voltage is switched ON
while gate is ON.
For this study, EPC tested parts in both fault modes
and found no significant differences in the withstand time.

Therefore, we will focus on FUL results for the remainder
of this discussion. It should be noted that up until the time
the FETs fail catastrophically, the short circuit can be fully
quenched by switching the gate LOW, an advantageous feature for protection circuitry design.
Two representative eGaN FETs were tested: EPC2203
(80 V), a 4th generation automotive grade (AEC) device, and
EPC2051 (100V), a 5th generation commercial grade device.
Both devices were chosen because they are the smallest
in their product families. This simplified the testing owing
to the high currents required for short-circuit evaluation.
However, based on simple thermal scaling arguments, the
withstand time is expected to be identical for other in-family devices. Results of this testing are shown in Figure 9.
To gather statistics on the withstand time, cohorts of
eight parts were tested to failure using this approach. Table 2
summarizes the results. EPC2203 was tested at both 5 V
(recommended gate drive) and 6 V (VGS(max)), with mean
withstand time of 20 μs and 13 μs respectively. Note that
the part survives less time at 6 V because of the higher
saturation current. EPC2051 exhibited a slightly lower
time-to-fail (9.3 μs) compared with the EPC2203 at 6 V.
This is expected because of more aggressive scaling and
current density of this device. However, in all cases, the
withstand time is comfortably long enough for most shortcircuit protection circuits to respond and prevent device
failure. Furthermore, the withstand time showed small
part-to-part variability.
The lower rows in Table 2 provide pulse power and
energy relative to die size. To gain insight into the relationship between these quantities and the time to failure, timedependent heat transfer was calculated to determine the
rise in junction temperature, ΔTJ, during the short-circuit
pulse. The results are shown in Figure 10.
The intense power density during the pulse leads to
rapid heating in the GaN layer and nearby silicon substrate. Because the pulse is short and heat transfer is
relatively slow, only a small thickness of semiconductor

100
ID-Drain Current (A)

the data sheet graph. The same applies to 1 ms pulse data
(purple and red triangles): all failures occurred outside of
the data sheet SOA.
Figure 8 compares SOA data between a commercial
power MOSFET (dotted lines) and an EPC2045 eGaN FET
(solid lines) with a similar rating. The secondary breakdown due to the Spirito effect described in reference [9] is
evident in the Si power MOSFET at drain voltages as low as
10 VDS for 1 ms pulses.
The data sheet SOA graph is generated with finite element analysis, using a thermal model of the device including all relevant layers along with their heat conductivity
and heat capacity. Based on transient simulations, the SOA
limits are determined by a simple criterion; for a given pulse
duration, the power dissipation must be such that the junction temperature does not exceed 150 °C before the end of
the pulse.
This criterion results in limits based on constant power,
denoted by the 45° green (100 µs) and purple (1 ms) lines in
the SOA graph. This approach leads to a datasheet graph
that defines a conservative safe operating zone. In power
MOSFETs, the same constant power approach leads to
an over-estimate of capability in the high voltage region
where failure occurs prematurely due to thermal instability
(Spirito effect).
However, from the perspective of the physics of failure,
it is evident from Figure 8 that, in certain cases, the eGaN
FETs can survive well outside the nominal safe zone, but
the operating margin decreases at higher drain-source bias
and longer pulse durations.

0.1
0.1

Limited by RDS(on)

BSZ070N08LS5
EPC2045
100 µs Pulse
100 ms Pulse
1
10
VDS-Drain-Source Voltage (V)

100

FIG 8 Comparison between a BSZ070N08LS5 MOSFET and an
EPC2045 eGaN FET safe operating area.

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