IEEE Power Electronics Magazine - December 2021 - 37

Efficiency SR Versus Body Diode
100
99.8
99.6
99.4
99.2
99
98.8
98.6
98.4
98.2
98
97.8
97.6
Pout (W)
2X UJ4C075018K4S LF SR 230 Vac
2X UJ4C075018K4S LF Body Diode 230 Vac
FIG 12 Efficiency comparison with LF leg using synchronous
rectification (Si Superjunction) and using Si superjunction body
diode.
More Cost-Effective Design (Diode on Slow Leg)
With the excellent performance from Gen 4 FETs the line
frequency leg (LF) can use diode rectification and still
achieves above 99% peak efficiency as shown in Fig. 11
and Fig. 12.
This will further reduce cost as Si diodes are much
cheaper than low RDS(on) Si superjunction MOSFET. Moreover,
as shown in Fig. 11, we can simplify the circuit by
using one diode rectifier bridge for the LF leg diodes D3, D4
and the pre-charge surge diode D1, D2. Therefore, Fig. 11
provides a more cost-effective design achieving both cost
and board size reduction with above 99% efficiency from
50% to 85% of the load.
Summary
Thanks to the excellent performance from UnitedSiC's Gen
4 FETs, 99.37% peak efficiency is achieved on a 3.6 kW CCM
TPPFC with only two UJ4C075018K4S devices. Detailed
loss calculation shows very small loss on Gen 4 FETs which
suggests viability of using smaller packages that can further
increase power density and reduce cost. Moreover, a costeffective
solution is proposed to replace expensive low
RDS(on) Si superjunction MOSFET with Si diode rectifier
and still achieve above 99% peak efficiency from 50% to 85%
load range. Gen 4 SiC FETs provides high efficiency, high
power density, low cost, and a very simple power design for
hard-switching applications like CCM TPPFC.
About the Authors
Ke Zhu (mzhu@unitedsic.com), Application Engineer,
UnitedSiC. Ke Zhu received his BS in Electrical Engineering
from Chongqing University in 2013, and MS in Electrical
& Computer Engineering from The Ohio State University in
2015 and joined UnitedSiC since then. He has 7 year's
research experience in SiC and GaN device evaluation,
design of high frequency, high efficiency and high power
density power electronics as well as EMI solutions for
WBG devices.
Anup Bhalla (abhalla@unitedsic.com) VP Enginering,
UnitedSiC. Anup oversees all product development at UnitedSiC
and became an investor in the company when he
joined in 2012. Prior to joining UnitedSiC, Anup held various
product development and marketing positions at Alpha &
Omega Semiconductor, of which he was a co-founder. He is
the author or co-author of nearly 100 patents through his
career at Harris, Vishay Siliconix, AOS, and UnitedSiC. He
received his bachelors' degree from the Indian Institute of
Technology, Delhi, and his Ph.D. from Rensselaer Polytechnic
Institute, both in Electrical Engineering.
Jonathan Dodge (jdodge@unitedsic.com), Senior
Applications Engineer, UnitedSiC. Jonathan received a
BSEE in Electrical and Electronics Engineering from Oregon
State University in 1992, and an MSEE in Electrical
Engineering from The University of Idaho, with an emphasis
in power electronics and digital design, in 2000. Jonathan
has experience in automated manufacturing testing, analog,
digital, and power electronics spanning 1.5- to 500-kW
power levels.
References
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[7] K. Yao, Y. Wang, J. Guo, and K. Chen, " Critical conduction mode boost
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[8] Z. Wang, S. Wang, P. Kong, and F. C. Lee, " DM EMI noise analysis for
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[9] https://info.unitedsic.com/gen4
December 2021 z IEEE POWER ELECTRONICS MAGAZINE 37
Efficiency (%)
500
1,000
1,500
2,000
2,500
3,000
3,500
4,000
https://info.unitedsic.com/gen4
IEEE Power Electronics Magazine - December 2021

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