IEEE Power Electronics Magazine - December 2022 - 55

M
easuring the gate-source voltages of wide
bandgap (WBG) devices in half-bridge converters
provides useful information about
susceptibility to crosstalk,
which can cause
uncontrolled cross-conduction and
excessive gate-oxide stresses. However,
parasitic elements of the
printed circuit board (PCB) and
device packaging can compromise
measurement accuracy, causing
unreliable results. Here we describe
how this shortcoming can be
addressed using devices in packages
that have a Kelvin source pin, allowing
a more accurate analysis.
Switching performance
is greatly superior to
that of silicon
MOSFETs, allowing
increased operating
frequency.
Introduction
The critical figures of merit for silicon carbide (SiC) and
gallium nitride (GaN) MOSFETs enable extremely compact
and efficient power converters [1], [2]. Switching performance
is greatly superior to that of silicon MOSFETs,
allowing increased operating frequency. However, the
faster switching transitions increase dv/dt and di/dt,
which can cause significant
ringing issues in the switching
loop [3]-[5], due to parasitic
effects in device packaging
and PCB layout. These remain
potential barriers to their
wider adoption in some
power converter applications,
requiring deep investigation
as presented in [6]-[9].
Figure 1 shows styled waveforms
when crosstalk event
happens in a half-bridge converter
[10]. During turn-on of
the active device (e.g., high-side
MOSFET, QH), the voltage rises
across the other device (e.g.,
low-side, QL or complementary
device), causing a charging
current to flow through its parasitic
gate-drain capacitance
and induces a positive spike in
its gate-source voltage (VGSL
).
False triggering can occur if
this voltage spike exceeds the
gate threshold voltage. On the
other hand, when turning off
QH, the spurious gate-source
voltage on QL could rise above
the maximum rating and hence
damage the gate oxide [11].
The amplitude of the spurious
gate voltage is determined
by the portion of displacement current due to the Miller
effect, which charges/discharges the gate-source capacitance
of the complementary device [12]. Some practical
solutions to mitigate spurious gate
voltage due to crosstalk phenomena,
are presented in literature, for
instance gate-assist circuitries to
actively control gate voltages are
discussed in [13]-[15]. Alternatively,
additional passive devices may
be introduced as presented in [16]
and [17].
In addition to board and package
inductances [3], [7], [11], the parasitic
inductance of voltage probes used for
gate-source voltage measurements
should also be considered [18], [19]. This article evaluates
the gate-source voltage trend during switching transients
by taking measurements at the accessible external pins of
the discrete power switches.
The gate-source voltage seen at the device die is then
predicted using analytical modeling of the power converter
topology [20]. The simulation results are confirmed using
experimental tests.
FIG 1 Simplified representation of VGS induced spikes during half-bridge switching transients.
FIG 2 (a) Half-bridge board under test. (b) Equivalent schematic.
December 2022 z IEEE POWER ELECTRONICS MAGAZINE 55
IEEE Power Electronics Magazine - December 2022

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