IEEE Power Electronics Magazine - June 2014 - 25

deposition of material in geographically distinct layers that
dc-dc 3-D Packaging Survey-Identified Important Markets
build on each other to form
0-10 W
11-50 W 50-250 W 251-500 W 501-999 W 1 kW+
a 3-D part. In contrast, tradiIndustrial
tional manufacturing, such as
Military/Aero
drilling, milling, and turning,
Smartphone/Tablet
is a subtractive process. As per
Server
the talk, additive manufacturPC
ing lends itself to the protoComms
typing of complex plastic and
Consumer
metal parts without the need
Transport/Auto
for intermediate tooling, rapid
design iterations, and building
fig 8 A joint survey by PSMA and the Tyndall National Institute identifies the dc-dc markets for
of printed fan bezels, complex
3-D packaging. (Figure courtesy of APEC 2014.)
chassis parts, heat-sink bobbins, and high-current metal
lers with integrated PowIRstage, and Texas Instruments'
interconnects. The study shows that metal and plastic printing
12-A synchronous buck regulator SWIFT TPS53915. For now,
machines are available with machine cost declining as matethe products announced supported the earlier version, but
rial costs plummet.
the suppliers intend to bring v1.3 interface on board soon.
The detailed road map for additive manufacturing is availOn the power-over-Ethernet (PoE) front, the focus was on
able in PSMA's technology report. It shows that the technolthe tripling of the power of PoE. Since the current power capaogy is here and is expected to cut development time and cost.
bility of 25.5 is limited in terms of applications it can address,
a new task force has been formed to investigate the possibilEmerging Standards
ity of doubling or tripling the PoE power under a new version
With Power Management Bus (PMBus) 1.2 gaining momencalled IEEE 802.3bt. In his presentation "Tripling the Power
tum, the PMBus Specification Working Group released the
of PoE-Opening New Opportunities and Creating New
updated PMBus 1.3 specification, also known as PMBus+.
Challenges," Faisal Ahmad, Akros Silicon's vice president of
Ratified by the adopters in early March, v1.3 brings
marketing, stated that the task force was exploring ways to
enhanced bus throughput and improved latency over the
provide 90-W PoE power using all four pairs in the standard
earlier version, and adds a new bus called adaptive voltage
Ethernet cable while maintaining safety requirements and
scaling (AVS) for controlling processor, application-specibackward compatibility with existing PoE equipment.
fied integrated circuit (ASIC), and field-programmable gate
Meanwhile, Ahmad noted that Cisco has already evolved
array (FPGA) voltages. The detailed specs were presented
PoE to Universal PoE technology with up to 60-W power to
in a paper titled "An Introduction to Revision 1.3 of the
enable even broader endpoint support like Cisco IP phones.
PMBus Specification" by Travis Summerlin of Texas InstruLikewise, Akros Silicon showed 60/90-W PoE powered device
ments and Mike Jones of Linear Technology.
(PD) controller AS1860 incorporating isolated high-speed
In short, v1.3 improvements include a 1-MHz bus speed,
digital communication to deliver up to 90 W to an isolated secfloating-point data format, and support for relative voltage
ondary side comprising four independent outputs. According
thresholds and global process calls, including zone read/
to Akros, the AS1860's 90-W capability is fully backward comwrite. In addition to enhancements to parts I and II of v1.2,
patible with IEEE 802.3af and IEEE 802.3at compliant PDs. In
the latest 1.3 spec also offers AVSBus interface for AVS as
summary, from components to systems, APEC 2014 has set
new part III addition. Per this presentation, AVSBus offers a
the tone for advancing the state of the art at all levels of power
50-MHz maximum bus speed and is behaviorally and electridesign. When we meet in Charlotte, North Carolina next year
cally similar to serial peripheral interface bus without chip
for APEC 2015, the bar will be much higher.
select lines. It comes under new part III. In essence, it is an
application-specific protocol that allows a load like a processor, ASIC, or FPGA to control its own voltage for power
About the Author
savings. The v1.3 working group members include Altera,
Ashok Bindra (bindra1@verizon.net) is the editor-in-chief
Analog Devices, Artesyn, Embedded Power Lab, Exar, Interof IEEE Power Electronics Magazine and a veteran writer
national Rectifier, Intersil, Linear Technology, Maxim Inteand editor with more than 30 years of editorial experience
grated, STMicroelectronics, and Texas Instruments.
covering power electronics, analog/RF technologies, and
At APEC this year, many companies introduced new
semiconductors. He has worked for leading electronics trade
power devices with on-chip PMBus interface. These include
publications in the United States, including Electronics, EE
Analog Devices' digital power controller (ADP1055) with
Times, Electronic Design, Power Electronics Technology,
integrated high-resolution high-speed analog-to-digital conand RF Design.
verters, International Rectifier's CHiL digital PWM controlJune 2014

z IEEE PowEr ElEctronIcs MagazInE

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - June 2014