IEEE Power Electronics Magazine - June 2015 - 53

tor devices, all require operation in a
package that is free of bond wires and
The PSMA presented
that minimizes parasitic interconnect
elements. The report shows that both
its technology report
of these challenges can be addressed
Embedded Substrates
on
3-D
power
with power packaging utilizing embedAt APEC 2014, the PSMA presented
ded substrate technologies.
developments and trends in 3-D
packaging with a
Today, as per the report, multiple
power packaging as part of the associfocus on embedded
embedded substrate technologies are
ation's technology roadmap [3]. This
available for power assemblies. Some
year, PSMA's Packaging Committee
substrate
of these include AT&S embedded comannounced a new report titled "Curtechnologies.
ponent packaging process flow (Figrent Developments in 3-D Packaging
ure 5) from AT&S, TDK's embedded in
with Focus on Embedded Substrate
substrate (SESUB) process flow (FigTechnologies." It focuses on available
ure 6), and Semikron's SKiN process. As more components,
materials and processes that can be best used for the creboth active and passive, are inserted into the substrate,
ation of advanced high-efficiency, high-density power prodthe designers must also overcome thermal issues. Conseucts. According to the cochairs of the PSMA Packaging
quently, it becomes more challenging to remove heat genCommittee, Ernie Parker of Crane Aerospace & Electronics
erated within a 3-D integrated system than from a planar,
and Brian Narveson of Narveson Consulting, the report is a
two-dimensional surface. As a result, the report discusses
comprehensive document that reveals the challenges comadvanced thermal management technologies which are key
panies will face to implement embedded substrate 3-D
enablers for 3-D packaging and PCB embedding.
power packaging to create the significantly higher power
The report, which was prepared under contract by
densities driven by the digital power demands.
LTEC Corporation with work subcontracted to Anagenesis
As per the report, the first challenge arises from the maturand Fraunhofer-Institute, is based on the Packaging Coming advanced deep-submicrometer semiconductor technolmittee's extensive research of over 750 articles and papers,
ogy, which can no longer reduce cost with the addition of more
analysis of 450 presentations/papers, and 30 industry exfunctions to the semiconductor die. This barrier was circumpert interviews. In addition, information was also obtained
vented through the development of wafer thinning that enabled
from ten industry conferences, workshops, and seminars.
through-silicon-via technology, resulting in the development of
The report contains 172 links and 394 citations.
2.5-dimensional and 3-D integration, which, in turn, facilitated
In summary, the PSMA report provides detailed analysis
heterogeneous ("more than Moore") integration. It enabled the
of substrates (organic and inorganic), components (active
power requirements of the digital load to increase several times,
and passive), thermal management, high-temperature dice,
within the same footprint, in a single generation. "Now the powpackaging technologies, interposers, and additive manuer industry is tasked with finding new ways to package power
facturing and laser fabrication.
sources that will meet this demand, but without increasing footprint," asserted Narveson.
Concurrently, power semiconductor technology is facing
About the Author
a "construction barrier" that prevents the realization of the
Ashok Bindra (bindra1@verizon.net) is the editor-in-chief
significant benefits the new technology can offer in terms of
of IEEE Power Electronics Magazine and a veteran writer
increased power efficiency and higher power density. The
and editor with more than 30 years of editorial experience
PSMA's 340-page report suggests that the new technologies,
covering power electronics, analog/RF technologies, and
including GaN, SiC, and gallium-arsenide power semiconducsemiconductors. He has worked for leading electronics
trade publications in the United States, including Electronics, EE Times, Electronic Design, Power Electronics Technology, and RF Design.
requiring higher current, up to four
modules can be connected in parallel
to deliver up to 200 A.

References
[1] R. Singh, "Silicon carbide switches in emerging applications," APEC 2015,
Industry Session 1, paper# ISI.6, GeneSic Semiconductor Inc., Dulles, VA.
[2] R. Singh and S. Sundaresan, "Fulfilling the promise of high-temperature
operation with silicon carbide devices," IEEE Power Electron. Mag., vol. 2,
no. 1, pp. 27-35, Mar. 2015.
[3] A. Bindra, "APEC sheds new light on emerging trends," IEEE Power
Electron. Mag., vol. 1, no. 2, pp. 20-25, June 2014.

FIG 6 TDK-EPC Corp.'s semiconductor embedded in substrate
(SESUB) process flow. (Image courtesy of TDK-EPC Corp.)

June 2015

z IEEE PowEr ElEctronIcs MagazInE

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - June 2015