IEEE Power Electronics Magazine - June 2017 - 71
Ultimate Goal Is to
Optimize for TCO
X-Y-Z Dimensions,
Interference to HighSpeed Routings
Component Cost,
Customization Cost,
Respin Cost
Efficiency
Density
Conversion and
Power Distribution
Scalability
Cost
Effectiveness
Sustainability
Design, Manufacturing
Complexity;
Time to Market
Flexibility Over
Power Specs
(Vo, Io, Transients)
Ability to
Leverage Technology
Advancement
Ease of Design
Fig 3 Google has crafted a new technology evaluation metric to optimize the total cost of ownership for new technologies and
designs. (Image courtesy of APEC 2017.)
the other when it comes to efficiency, density, performance, and cost.
With adoption rates rising for wide-bandgap devices,
standardization took another step forward with the
announcement of the GaN Standards for Power Electronic Conversion Devices Working Group (GaNSPEC
DWG) in session #IS09.1 by Texas Instruments' Technology Innovation Architect Stephanie Watts Butler. Comprising GaN manufacturers, users, researchers, and
agencies such as the Joint Electron Device Engineering Council (JEDEC) and the IEEE Power Electronics
Society, the GaNSPEC DWG is seeking to create standards and guidelines for test methods, reliability and
qualification procedures, and data-sheet parametrics
for GaN-based power conversion devices. By the up coming Workshop on Wide-Bandgap Power Devices,
30 October-1 November 2017, in Santa Ana Pueblo, New
Mexico, the group intends to generate proposals for
guidelines to lead into JEDEC standards.
On the magnetics front, next-generation ferrite material
for high-frequency GaN and SiC applications was described
by researchers from SUMIDA Components and Modules in
dialog session paper #D09.7. Written by Herbert Jungwirth, Michael Schmidhuber, and Michael Baumann,
the paper disclosed a novel ferrite material for high-frequency applications. While the special compounds used in
the construction of the new ferrite core material were not
discussed, the researchers claim that the new material is
HIPS
Input
Voltage
GaAs
Die
CMOS
Die
VDD
PWM1
UFET1
Drivers
LFET1
Bypass Capacitors
Inductor
Output
Voltage
UFET2
PWM2
LFET2
Inductor
Capacitors
Fig 4 Sarda's HIPS integrates GaAs FETs, CMOS drivers, and passive components in a single low-profile QFN package using 3-D techniques. (Image courtesy of APEC 2017.)
June 2017
z IEEE PowEr ElEctronIcs MagazInE
71
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