IEEE Power Electronics Magazine - June 2019 - 45

Device A (SiC)

Thermal Impedance, Zth,jc (°C/W)

1

0.1
Pd =
Id × Vd

0.01
Vendor SPICE
LTEC ExtZth

0.001

Heat Source
Rc1
∆Tj

SiC Substrate
Paste PKG
Rc2 Rc3 Rc4 Rc5 Rc6 Rc7 Rc8

Cc1 Cc2

Cc3 Cc4

∆Tc

Cc5 Cc6 Cc7 Cc8

Synthesized Cauer-Equivalent Thermal Circuit
(b)

TCAD Sim
Data Sheet

No Data
Region

0.0001
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00
Pulsewidth, tp (s)
(a)
FIG 10 The thermal impedance Zth of SiC device A as a function of (a) the on-time pulsewidth tp and (b) the extracted Cauer thermal-circuit model. TCAD: technology computer-aided design; PKG: package.

during an SC transient, the temperature dependence of
the materials' thermal characteristics is represented in
the proposed electrothermal model, a feature that is not
included in conventional Zth modeling.
A specific result for the device A SiC MOSFET is shown
in Figure 10, where 1) Zthjc as a function of pulse time tp and
2) the synthesized Cauer thermal network are illustrated.
This electrothermal model is used in conjunction with
drain-current waveforms [21]-[23] to simulate and evaluate the SC event-induced temperature rise in the 1-100-ns
range. The results are presented in Figure  11 for the 2G
and 3G SiC MOSFETs of device A's manufacturer. The
transistor temperatures Tj, determined from the manufacturer-provided electrothermal simulation program with
integrated-circuit emphasis (SPICE) model and our analysis (yellow), are indicated in Figure 11. For the 3G transistor, our proposed model predicts Tj ~1160 °C at t = 7 ns,
which contrasts with estimates using the manufacturer's
model (Tj ~440 °C). Note again that direct measurement of
the transistor's internal temperature at such short on-times
(< 10 ns) is not feasible and, generally, physics-based numerical-device simulation is used [22], [23]. In this respect, the
proposed Zth model matches the manufacturer's data for t ≥
100 ns, and our results are well in line with published simulations [21], thus, validating our approach.
As mentioned previously, performance improvements, raw-wafer and epilayer quality, and cost reduction drive SiC transistor technology development,
while continuously reducing the transistor-unit cell
size (Figure 3). Die-size reduction, however, brings
a concomitant increase in thermal impedance (Z th ?
1 ⁄area) and, hence, self-heating-induced temperature

rise. This shortens the SC withstand time tscf -the
time needed to reach the critical-fail temperature, as
illustrated in Figure 11 for the SiC device A transistor
(3G) and its predecessor (2G) from the same vendor.
As shown, the time to reach the aluminum melting
temperature (~660 °C) is reduced from ~5.5 ns for the
2G transistor to ~2.5 ns for the 3G device. Observe that
at the failure time tscf ~7 ns for the 3G transistor, the
critical temperature is Tcrit ~1,160 °C, which is close to
the SiC intrinsic temperature.
In Figure 12, the trend line of the effect of SiC transistor downscaling on the SC time to failure tscf is further
illustrated, summarizing published and measured data for
devices from manufacturers A and B and for the case of
constant RON (~80 mX).
For a practical circuit design, the SC withstand time tsc
(< tscf ), with adequate margin, should be specified considering material and process-induced fluctuations and environmental and circuit operating conditions. Although not
shown here, preliminarily considering tsc ~tscf/2 and consulting with the transistor manufacturer are recommended.
The reduction of SiC transistor robustness (or withstand
time) with scaling is a fundamental tradeoff to be considered when evaluating new transistor generations and, also,
for the design of faster protection circuitry [24], [25]. In
other words, if SC endurance margin is a priority, using a
nonshrunk device rather than one from a newest generation
could be a choice to consider.

Conclusions
Deep physical structure and material analysis were used
to extract transistor layout, vertical device structure, and
June 2019

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IEEE Power Electronics Magazine - June 2019

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