IEEE POWER ELECTRONICS MAGAZINE z June 2019 Cbulk + Clamp Cc R2c R1b R2b VBULK_RES VBULK COMPS AC_RCF ISNS IS_REF 10-V Start-up LDO Digital OptiMode SW DGND Active Clamp Driver VSOUT AC COMPS Active Clamp FET BOOT_CL Cbst GND Clock Gen Bandgap NTC_RCF NTC COMP SV LDO QR COMP Main Switch Driver Gate Rsense Primary FET CVSOUT Cv10 FB RFB VSOUT VAUX_S Temperature VSOUT DSc x V10 Regulator* FIG 3 An active flyback converter using controller chip SZ1101. (Source: Silanna Semiconductor; used with permission.) VBULK_S CLMP_S VBULK R1c ADC 52 ISENSE COMPS Ca R2a R1a Auxiliary Primary VOUT Sync Rec Cout Secondary FET Secondary VOUT