IEEE Power Electronics Magazine - June 2021 - 20

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small-signal transistors. While SiC HV transistors
exhibit superior advantages over their silicon counterparts,
the SiC small-signal transistors are
decades behind the CMOS transistors in the lastest
Si BCDMOS technology in terms of device performance
(e.g., transconductance and switching delay
time). While high-temperature applications do
require ICs comprised of all SiC transistors, the
afore mentioned motor drive and granular power
processing applications do not necessarily need to
operate at a junction temperature higher than 150°C.
In other words, SiC power ICs may need to take a
technological pathway different from that of SiC
high-temperature ICs. It is worth exploring IC technologies
that effectively combine SiC HV power transistors
with low-cost and high-performance Si CMOS
circuits. The author recently proposed two potential
SiC power IC pathways along this line of thinking for
the purpose of stimulating more discussions on the
subject among the researchers [15].
Figure 4 illustrates a SOI-on-SiC (SOISiC) power
Trusted · Innovative
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IC concept that comprises one or more SiC LDMOS
power transistors formed in a SiC wafer and Si
CMOS circuitry formed in an SOI thin film on top of
the SiC wafer. The fabrication process is similar to a
SiC BCDMOS process with one additional processing
step of forming a CVD polysilicon thin film on
top of a thick oxide layer on the SiC wafer after the
formation of deep junctions such as Deep-N-Well
(DNW), P-Body, and N-Drift regions shown in Figure 4.
The polysilicon film is then recrystallized by laser or
high-temperature anneal to become a single crystal
thin film for making high-performance CMOS circuitry.
Laser annealing of semiconductor wafers is a
widely used processing technique in IGBT and
CMOS image sensor fabrication. After forming the
SOI layer, gate oxidation, polysilicon gate, drain/
source implant, and metalization steps will follow
to complete the SiC power transistors and the
CMOS transistors at the same time. The addition of
SOI CMOS transistors only requires a few additional
processing steps to the standard SiC MOSFET fabrication
process, making the SOISiC power IC technology
potentially cost effective. The SiC MOSFET
shown in Figure 4 is a LDMOS, but can be replaced
with a vertical VDMOS transistor to make SiC
SmartDiscrete products. A SiC SmartDiscrete MOSFET
with monolithically integrated active gate drive
and protective circuits can be an attractive option to
minimize the parasitic inductance of the external
gate driver and/or provide ultrafast desat protection
under short circuit faults, which are among the
major challenges in using discrete SiC power MOSFETs
today.
Figure 5 illustrates yet another approach of
making SiC power ICs by using a SiC/Si heterogenic
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IEEE Power Electronics Magazine - June 2021

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