IEEE Power Electronics Magazine - June 2021 - 26

number of switching devices, making the MMC implementation
challenging for any RTS.
Namely, in a system with a high number of switching
devices, every combination of switches being on/off generates
a unique system state. Recognizing and memorizing
every state the system can be found in imposes tremendous
computational burden upon the RTS. Therefore, minimization
of switching elements, used to model an arbitrary converter,
represents one of the key aspects in obtaining an
efficient real time model.
As presented in [9], a cluster of FB SMs can be modelled
as in Figure 4, where controlled voltage sources v1 and v2
represent a combination of SM switching signals, provided
by the controller and captured by the RTS, and instantaneous
values of SM capacitor voltages, leading to the MMC
model given in Figure 5. At its ac terminals, the MMC is
interfaced with a three-phase voltage source through a
series connection of an inductor and resistor. Thus, the
same model can be used for real-time simulations of an
MMC connected to an ac grid, ac machine or any other converter
through the inductive interface (e.g., low-frequency
transformer), making it general and extremely flexible.
Table 1 provides parameters of the grid-connected conNumber
of
Description
Analog Inputs
Analog Outputs
Digital Inputs
Digital Outputs
SFP Ports
Channels/Connectors Voltage Range
-10 V ... 10 V
-10 V ... 10 V
3.3 V or 5 V
3.3 V or 5 V
16
16
32
32
4
FIG 3 PLECS RT Box 1 and its characteristics.
N.A.
verter, operating in the rectifier mode, used for realization
of the digital twin described hereafter. According to Table 1,
the analyzed converter comprises 6 × 8 = 48 FB SMs, meaning
that an RTS running the model from Figure 5 must
be able to handle up to 48 × 4 = 192 switching signals,
which far exceeds the 32 DIs available on the RT Box 1
presented in Figure 3 and referred to as HIL unit onwards.
However, voltages v1 and v2 from Figure 4 can be calculated
in an independent HIL unit for a branch comprising up to
32/4 = 8 SMs. Conveniently, six independent HIL units can
be used for calculation of relevant branch voltages, and
these will be referred to as the Branch RT Boxes. Nonetheless,
the model from Figure 5 needs to run on seventh HIL
unit, being referred to as the Application RT Box, leading to
the structure presented in Figure 6.
Owing to the insufficiency of the SFP ports on the AppliDC+
ph+
C1
DC-
DC+
S2
S3
+
Σ
iC
S1
S4
DC-
Vectorized
(1..N)
Non-Vect.
FIG 4 Branch model derived in [8]. Irrespective of the SM type (HB or FB), the branch
model remains unchanged.
26 IEEE POWER ELECTRONICS MAGAZINE z June 2021
V
vC
×
Σ
u - 1
×
Σ
A
+
-
i2
v2
ph-
ph+
Σ
(1)
III
u - 1
×
×
Σ
+
-
A
v1
i1
CN
DC-
(N)
(1)
iC,1
DC+
(N)
iC,N
ph-
cation RT Box rear panel, a daisy chain illustrated on the
right-hand side of Figure 6 must be created.
Moreover, one can notice the two types of
boards interfaced with the Application and
Branch RT Boxes, respectively, along with
the so-called SM card. The need and derivation
of the abovementioned components is
addressed in the next section.
Detailed MMC HIL Description
It is straightforward to conclude from Figure
4 that calculation of branch voltage components
v1 and v2 requires Branch RT Boxes
to capture switching signals being delivered
to the real physical SMs. Therefore, a certain
interface between the Branch RT Box and the
employed MMC controller must be ensured.
The SM being used as a reference point
throughout the HIL realization process, and
discussed in detail in [10], can be seen on
the left-hand side of Figure 7. The develop ed
MMC SM consists of two parts - powerboard
(the bottom one) and control-board
(the top one). The control-board hosts all
the logic (intelligence) related to the SM
operation, which is an important detail in
the digital twin development.
IEEE Power Electronics Magazine - June 2021

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