IEEE Power Electronics Magazine - June 2021 - 41

Al flowed from the source electrode,
shorting the gate electrode. The transistor
temperature exceeded the Al
melting temperature (Tm~660 °C).
This fact is used to extract the thermal
impedance under the SC conditions.
The short-circuit failure mode
and critical
temperature ()T ,j crit
of
Need to look inside
the transistors to
understand their
potentials and
limitations.
the evaluated vendor D MOSFETs
are controlled by the transistor physical
design. The transistor does not
explode or burn and turns off " quietly " as the gate-source
electrode is shorted by the melting of the aluminum. This is
a desirable feature that prevents further destructive damage
at the system level.
Estimating the Transistor Temperature
Estimating the transistor internal temperature Tj
is a prerequisite
for circuit design and reliability compliance margin
verification. As a first order estimate, the transistor temperature
is proportional to the dissipated power times the thermal
impedance. Therefore, determining and modeling of
the effective thermal impedance ()Zth
under SC conditions
is essential.
Typically, in the vendors' datasheet, Zth
T ,maxj
and associated
SPICE models are extracted at low temperature (less than
the spec
150-175 °C); however, during a SC pulse the
transistor temperature exceeds several hundred degrees
[7]-[9], which invalidates the low-temperature extracted
Z .th
ature, T ,j
In this work, since the heat generation source temperis
not directly accessible, physical analysis and
computer aided design (CAE) numerical simulations are
used in conjunction with SC pulse test for modeling and
synthesizing the thermal impedance Zth
as described in [2].
Figure 12 shows an example of the extracted thermal
impedance Zth and the synthesized Cauer electro-thermal
1
Vendor Datasheet
Vendor SPICE
LTEC SC Eval. ExtZth
0.1
EMC + AI
Heat
Source
SiC Bulk
0.01
Die Attach
0.001
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
Pulse Width, tp (µs)
FIG 12 Extracted and modeled thermal impedance for device from Vendor D.
June 2021 z IEEE POWER ELECTRONICS MAGAZINE 41
Pkg Lead
Frame
Cm
Ch
Rm
C1 R1
R2
R3
R4
R5
C2
C3
C4
C5
Tc
Tj
Pd
SPICE model for the SiC transistor of
Vendor D. In the graph, the vendor's
provided datasheet (square marks)
and the SPICE model results (dash
line) are shown. The red triangle
marks and line show our measured
and modeled results under a SC condition.
Clearly, the vendor's datasheetbased
Zth
underestimate the thermal
impedance (almost a 3x factor at
),
10 sn and this results in overestimation
of the SC endurance time.
A practical application is shown Figure 13, where (a)
the SC drain current measured and model-simulated
waveforms, and (b) the transistors simulated temperature
rise using the extracted Zth
electrothermal model,
are shown for the second and third generation SiC transistors
from Vendor A [2]. For these transistors, the cell
pitches (size) are 11 mn and 6mn for the second and
third generations, respectively. For the third generation
device, the average dissipated power is P 88kW
in the t 05 s-n=- interval. At t 7sn=
j + c
d =
, T 1160 C and
c
j
+
T 800 C are reached in the third and second generation
transistors, respectively. This comparison clearly
shows that device downsizing/downscaling increases
the self-heating effect; increasing the thermal impedance.
The Table in Figure 13 summarizes the estimated
Tj
temperature rise considering the vendor's model and
our model. Clearly, i) it is necessary to physically model
Zth
to obtain reasonable meaningful results. ii) For the
second and third generation devices, of the same manufacturer,
the critical temperatures (at failure) are approximately
the same, namely, T
j,crit + 1150 C (close to the
c
SiC intrinsic temperature) in this technology. And iii) the
transistor size reduction effect results in the reduction of
the endurance time ().
t
sc,f
Thermal Impedance, Zth (°C/W)
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