IEEE Power Electronics Magazine - June 2023 - 66

their much faster switching transitions
result in even more extreme
commutation dv/dt and di/dt than
their silicon predecessors. The common
advice offered by generic application
notes on power electronic
PCB layout is to " minimize parasitic
inductance as much as possible. "
However, the best way to do that is
not always clear. Moreover, not all
conductive paths necessarily need
to be lowest possible inductance:
consider the interconnection to an
inductor-clearly there will already
be inductance in that path.
It is of course impossible to minimize all interconSince
design of the power loop
Depending on the
geometric relationship
between source and
return current, the
mutual inductance can
change the sign
resulting in subtraction
rather than addition.
nect inductance, and simultaneously eliminate all nodeto-node
capacitance on a PCB. The key to successful
PCB layout is therefore to understand where the impedances
really matter in switch-mode power electronics,
and how to mitigate any undesired consequences of this
inevitable impedance.
An additional complicating factor is that PCB layout not
only involves optimizing the electrical interconnection, but
often requires thermal pathways that conflict with electrical
optimization goals. Even mechanical structures like
heatsinks, when applied to the PCB, and separated only by
a thin thermal interface material (TIM) can behave like an
additional electrical plane of the PCB assembly, and interact
with the switching nodes of the circuit.
This article begins by explaining the fundamentals:
what is really happening during a switching transition,
what is the cause versus effect of the transient voltages
and currents we see, and where exactly is the current
flowing. When we think about current flow, we often forget
to consider the return path, which is critically important.
An additional key concept is how we think about
inductance: it is often viewed as individual inductive
elements that all add-up around a loop. But they don't
necessarily all add-up: depending on the geometric relationship
between source and return current, the mutual
inductance can change the sign resulting in subtraction
rather than addition. The concepts of loop, partial and
mutual inductance help us to explain and understand
this interaction.
Next, different power stage layout options are presented,
along with the tradeoffs involved with each. The
overall goal here is to understand the best ways to minimize
power-loop inductance. With traditional throughhole
transistors mounted perpendicular to the PCB, the
inductance of the transistor package is independent of
the PCB layout because they are at right angles. For surface-mounted
packages (SMT), the package inductance
itself is a function of how the return-path is routed, so
there are more layout options and alternatives to improve
overall performance.
66 IEEE POWER ELECTRONICS MAGAZINE z June 2023
includes thermal as well as electrical
path optimization, the options and
tradeoffs of top versus bottom-side
cooled transistor packages are covered.
Finally, the design, layout and
routing of the gate drive circuit, along
with its " hidden " current paths are
explained.
What Problem are We Trying to
Solve?
The physical layout and packaging of
power electronic circuits adds " parasitic "
circuit elements RParasitic,
CParasitic, and LParasitic. These parasitic elements can cause
unexpected behavior and unintended consequences, circuit
malfunction, EMI, oscillations, and in severe cases, crossconduction
or " shoot-through " that can lead to transistor
failures. Resistive parasitics are comparatively easy to
understand-especially for dc current. The solution to minimize
parasitic resistance is to use more copper-increase
the total current-carrying cross-section. With high-frequency
ac currents, the situation is more complex due to skin
effect. For PCB integrated magnetics, the skin and proximity
effects need to be carefully considered, but that is outside
of the scope of this article.
The concept of parasitic capacitance is also straightforward.
Especially in a structure like a PCB, where the
copper layers form parallel plates with thin dielectric layers
in between. We can use simple 2D tools to estimate
the C ≈ ε0 εR (area / spacing) and we can easily estimate
capacitance per area for a given layer-stackup. As we
will see later, sometimes the capacitive coupling paths
are through components rather than the PCB itself. How
many pFs are too much versus acceptable? This will be
covered later as well.
Parasitic inductance is different: basic circuits classes
teach us to think of inductors as discrete elements that
sum like resistors in series. However, in more advanced
magnetics courses, we learn they interact with each other
through mutual inductance, which can either increase or
decrease the total inductance, depending on the geometry
and direction of current flow. Also, we often don't have a
good estimate of layout inductance, or know the magnitude
of di/dt to expect from our switching circuit-how
much will cause problems?
These layout issues are not new to power electronics,
but GaN transistors with low charge and no reverse-recovery
make switching transitions even shorter. Fast-switching
transistors primarily cause two inter-related issues. The
high transconductance of GaN, combined with its low gatecharge,
can result in extremely fast switching dID/dt. The
fast dID/dt leads to high peak currents as the capacitance
of the switch-node is rapidly discharged-the resulting
C dVDS/dt adds to the load current. And high peak switching
IEEE Power Electronics Magazine - June 2023

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