IEEE Power Electronics Magazine - June 2023 - 73

best-case TO-247 layout results in about 15 nH of total loop
inductance as shown in Figure 11.
Applying this knowledge to the expected di/dt, we see
that the resulting overshoot voltage would peak at 135
V. This may exceed the design limits: for example, if the
nominal bus voltage is 400 V, and the design rules mandate
that peak voltages are ≤80% of rated voltage, then the 535
V peak will exceed that even for a 650 V rated transistor.
This suggests that the solution for using TO-247 packages
and keeping overshoot voltage below 480 V is to slow-down
the switching, by increasing the turn-on and turn-off gatedrive
impedances for example. Slowing down switching will
of course also increase switching loss-which takes-away
from the benefit of using GaN transistors in the first place.
The surface-mount TOLL with single-sided returnpath
is the next-best option for low power-loop inductance.
Figure 11 shows that its layout inductance with 9 A/
ns applied would result in an 81 V overshoot-just at the
design goal of 480 V peak assuming a 400 V bus. By adding
the parallel return-path on the gate-side (the TOLL dual
return-path), the loop inductance is now low enough that
the overshoot voltage is 54 V, providing some additional
margin so that even if the bus is pumped-up to 420 V, the
added 54 V overshoot will stay below the 480 V design goal.
All three of the bottom layouts in Figure 11 have sufficiently
low loop inductance, providing suitable options for either
top or bottom-side cooled packages.
Considerations for Gate-Drive Layout
GaN transistors have low threshold voltages, typically in the
range of 1-2 V. In addition, the fully-ON VGS is in the range of
3.5-5 V (depending on the gate technology), and the transconductance
of the transistor, as well as its gain-bandwidth,
are quite high in the active region. This set of characteristics
makes it imperative that the gate-drive loop must be lowimpedance,
otherwise CGD dVDS / dt current injected through
the " Miller " capacitance (CGD) will influence the gate voltage,
resulting in ringing, overshoot, potentially high-frequency
oscillation, and spurious turn-on leading to
potentially destructive cross-conduction or " shoot-through. "
One of the biggest challenges is keeping the gate off
when a fast-rising dV/dt appears on its drain voltage. It is
all but impossible to make the gate-drive loop low enough
impedance with separately-packaged transistor and
driver. This is primarily why negative gate-bias is used
in discrete designs: to provide sufficient margin so that
gate bounce voltage does not exceed the threshold during
switching transients.
We can use the concepts discussed earlier regarding
power-loop inductance to optimize the gate-loop as well.
Figure 12 shows an example layout of a gate-drive IC connected
to a TOLL packaged transistor. Just like in the
optimized power-loop, the concept here is to use a pair of
over/under PCB layers with close-spacing to maximize the
mutual inductance (minimize loop area and gate drive loop
inductance). This example includes the RC network used
with the gate injection transistor (GIT) version of the GaN
HEMT, including separate RON and ROFF for the separate
source and sink pins on the driver.
The 6-pin gate-driver package U1 is on the far right with
its supply bypass capacitor C3. The 4 RC components are
in-line to the gate pin of the GIT, all on the surface-layer
(red). The Kelvin Source (KS) pin of the GIT is the reference
point for the return-path, which is defined by the
copper-pour polygon on layer 2 (dark brown color). The
return-path terminates back at the " GND " connection of
FIG 11 Summary of power-loop inductance and implications.
June 2023 z IEEE POWER ELECTRONICS MAGAZINE 73
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