IEEE Power Electronics Magazine - June 2023 - 75

bus voltage. Moreover, the dv/dt across this capacitance
is the fast dv/dt of the switch-node. The simplified parasitic
PCB capacitance is drawn in red on the schematic in
Figure 14. This type of layout will most likely experience
problems due to the charge injected into the gate-drive
circuit on every switching edge.
This is an example of one of the compromises or tradeoffs
that often must be made during a PCB layout: optimizing the
gate driver layout results in a less-optimal power-loop. Conversely,
optimizing the power-loop produces gate drive layout
problems. There is another approach to the gate-drive
layout to consider: keep the double-sided return-path for the
power-loop and move the gate-drive circuit to the back-side
of the PCB. The gate drive loop would then need to include
vias to connect to the transistor. Side-by-side vias provide a
reasonably low-impedance, and the back-side of the board
is farther away from the ground-plane. This seems like a
promising approach, but there is still another layer to work
with that can provide a unique solution.
Using a Driven Faraday Shield
With the gate-drive circuit on the back-side of the PCB as
shown in Figure 15, layer 3 is available as a return-plane.
The goal here is to minimize the effect of the common-mode
capacitance between the gate-drive circuit and the bus
ground plane. If I add a local plane on layer 3 (cyan color),
and connect that to the switch-node, the value of the capacitance
changes and also where the current comes from to
charge and discharge that capacitance.
The switch-node is the " local ground " for the highFIG
13 A more detailed look at the gate-drive loop routing
from Figure 12.
side. Adding the plane on layer 3 is really no different
than the return-plane added to the gate-drive circuit
in Figure 12, the capacitance between the circuit and
the plane will be the same. However, the layer 3 plane
shields the gate drive circuit from the problematic
capacitance to bus ground. The capacitance to bus
ground doesn't go away, but it is now between two lowimpedance
planes rather than coupling to the gate-drive
circuit and its components. Thus, the gate-drive circuit
only " sees " capacitance to its own local common, not to
the bus ground plane. The current necessary to charge
and discharge the inter-plane capacitance therefore
comes directly from the low-impedance switch-node,
completely bypassing the gate-drive circuit [2].
FIG 14 Double-sided return-path interferes with gate-driver routing and adds common-mode capacitance-not recommended.
June 2023 z IEEE POWER ELECTRONICS MAGAZINE 75

IEEE Power Electronics Magazine - June 2023

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - June 2023

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