IEEE Power Electronics Magazine - June 2023 - 76

Avoid driving the Faraday shield from the actual gate
driver ground-the Kelvin source (KS), rather than the
switch-node. While the small voltage bounce between S
and KS is insignificant compared to the other problem
this connection would cause, connecting the shield to KS
would cause all of the transient charge/discharge current
to flow through the KS bondwire(s). This would result in a
v = L di/dt reaction voltage that would appear as a differential
gate-drive signal. This can be a problem not only for
shield capacitances like this, but even for " unintentional "
capacitances, like the capacitance across any component
connecting the high-side circuit to bus ground.
Figure 16 depicts a typical example. The high-side gatedrive
circuit is capacitively-coupled to the low-side ground
through a signal isolator, and a dc-dc transformer (or alternatively
the junction capacitance of a bootstrap diode).
While these are typically only a few pF, there are examples
of dc-dc converters for gate drive that have more than 50
pF of capacitance across the isolation barrier. As shown
on the right of Figure 16, when the half-bridge is capable of
switching 400 V in a few ns, every pF is important. At 100
V/ns switching slew-rate, each pF results in 100 mA peak
common-mode current. The injected current spike then has
to return to bus ground through the low-side circuits, and
along that path, it could cause glitches in the logic or other
circuits. There is really no way to completely eliminate this
capacitance, so the best approach is to think about where
the return current will flow, and to minimize any effect-
make sure the return current has a low-impedance path
back to bus ground. Note that these capacitive effects can
be just as much a problem for integrated driver + transistor
as a discrete design-it all depends on the interconnection
inside the integrated driver + transistor.
To better understand the problem caused by the parasitic
capacitance charge/discharge current, consider the system
shown in Figure 17. The switch-node is the low-impedance
driving-point (driving the fast switching transition), shown
in red. In addition, everything in orange is also connected
to this node. The difference is that everything in orange is
driven indirectly-through the KS pin of the transistor. The
KS pin is only intended to be a part of the differential gatedrive
loop, and it is commonly just a single bondwire like
the gate. Due to the proximity inside the transistor package,
G and KS bondwires have low loop area and mutual inductance
helping to minimize overall gate-loop inductance.
However, when the current through the KS bondwire
is NOT common to the gate bondwire, there is no mutual
inductance cancelation and therefore a differential-mode
voltage will be generated within the gate-loop. As the
switch-node voltage rises, the voltage drop across KS bondwire
subtracts from the applied gate driver voltage, and
thus slows-down the switching transition. This effect can
essentially cancel the benefit of the Kelvin source package
by slowing switching speed much in the same way that
common-source inductance slows switching speed in a
conventional 3-pin transistor package.
An additional concern illustrated in Figure 17 is
spreading out the switch-node. It is best to keep the
switch-node compact to: 1) keep the capacitance minimized,
and 2) prevent it from radiating and capacitively
coupling to other parts of the circuit. Rather than placing
the gate-drive dc-dc converter on a separate board, it is
best to put that function right next to the power stage-
on the same PCB as the half-bridge.
The situation in Figure 17 should be avoided. Routing
the orange traces all over the system causes distributed
FIG 15 Driven Faraday shield to mitigate the common-mode capacitance problem.
76 IEEE POWER ELECTRONICS MAGAZINE z June 2023
IEEE Power Electronics Magazine - June 2023

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