IEEE Power Electronics Magazine - March 2015 - 25
R ^ t h = R 0 ^a + b ln 6 t @h .
(1)
In (1), a, b, and R 0 are parameters use for fitting a
curve to the data points and are extracted from the measured R DS^ONh time-series for each individual part. Using
these fitted curves, it is possible to extrapolate the time
at which the R DS^ONh will exceed the failure limit, even if
this time is well beyond the actual measurement time. Figure 5(a) shows representative data at 150 cC. The (extrapolated) time to fail for each part is indicated by a solid dot in
a Weibull plot [8]. The data for each voltage/temperature leg
were fitted to a three-parameter Weibull distribution using
maximum likelihood estimation (MLE) [9]. The MLE also
yielded 90% confidence intervals on the fit parameters.
The Weibull fits were used to calculate various statistical quantities, such as the mean time to failure (MTTF),
and the time at which a certain percentage of the parts are
expected to fail (TF%). The latter is shown in Figure 5(b)
for three different time to failure (TTF) percentages:
1) 1%, 2) 0.01%, and 3) 1 ppm. The diamonds indicate the
MLE, while the error bars give the uncertainty resulting
from the 90% confidence intervals on the Weibull parameters. At 100 V (the maximum rated VDS), the expected time
for 1 ppm failure rate from R DS^ONh shift exceeds 20 years.
The MTTF versus VDS for all three temperature legs in
this article is shown in Figure 6(a). The raw data (resulting
from Weibull fits) is indicated by solid dots. The error bars
indicate 90% confidence intervals arising from statistical
uncertainty in the Weibull fits. The solid lines are second-
MTTF Versus VGS
1030
MTTF (s)
1025
1020
1015
1010
Ten Years
5
10
5
5.5
6
Gate Bios (V)
(a)
6.5
7
FIT Rate Versus VGS
105
FIT Rate (Number/109 h)
a dynamic upward shift of the on-resistance ^ R DS^ONhh [7].
The shifting increases with drain bias and, at high enough
bias, the part will eventually fail when the resistance
exceeds the data sheet limits. The effect is caused by electron trapping near the conductive channel (two-dimensional
electron gas) and in the deep buffer layers of the GaN epitaxial film [8]. Control of the near-surface traps and the lateral and vertical electric fields is necessary to mitigate
dynamic R DS^ONh shifting.
To quantify the effect, a matrix of HTRB tests at accelerated drain voltages and at three different temperatures
(35, 90, and 150 cC) was conducted. Each leg consisted of
32 eGaN FETs, and the drain voltage during stress ranged
from 100 to 130 V in 10-V increments. These tests were
performed on two 100-V device types: 1) EPC2001C and
2) EPC2016C. Note that within the same voltage family of
eGaN FETs, the dynamic R DS^ONh shift is the same when
normalized by the initial R DS^ONh . A total of 18 such temperature/voltage legs were included in this article. During
the HTRB stress, the R DS^ONh of each part was monitored
in situ at regular intervals in time. Each readout cycle consisted of a 43-s dc stress, followed by an R DS^ONh measurement 2 s after drain bias was removed. This leads to an
effective drain stress duty cycle of over 95%. R DS^ONh has a
predictable dependence on time, increasing proportionally
to the logarithm of the stress time.
1 FIT
100
10-5
10-10
10-15
10-20
5
5.5
6
Gate Bios (V)
(b)
6.5
7
fig 7 (a) The mean time to gate failure versus gate voltage at
150 cC. Ten years is indicated by the dashed black line. (b) The
FIT rate versus gate voltage at 150 cC.
order polynomial fits to the data; these are merely interpolated values and have no physical significance. The failure rate is strongly accelerated by drain voltage and only
weakly affected by temperature between 35 and 150 cC.
At VDS^maxh (100 V), the MTTF is orders of magnitude
beyond the ten-year line, independent of the operating temperature. Figure 6(b) shows the failure in time (FIT) rate,
derived directly from the MTTF [11]. The FIT rate is below
one failure per billion device hours at 110 V and is negligibly small at VDS^maxh .
Gate Acceleration
There are several mechanisms that can contribute to failure
during high-temperature gate bias (HTGB) stress at high
gate voltage. These included dielectric failure, gate sidewall
rupture, and an increase in off-state drain leakage resulting
from gate stress. The dominant gate failure mechanism for
eGaN FETs is an increase in off -state drain leakage
induced by extended operation at high gate voltage and is
highly accelerated with gate voltage.
March 2015
z IEEE PowEr ElEctronIcs MagazInE
25
Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - March 2015
IEEE Power Electronics Magazine - March 2015 - Cover1
IEEE Power Electronics Magazine - March 2015 - Cover2
IEEE Power Electronics Magazine - March 2015 - 1
IEEE Power Electronics Magazine - March 2015 - 2
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