IEEE Power Electronics Magazine - March 2015 - 30

1
UB
B \ (U B) 3/2 .

tive bias on the gate with respect
to the source, or when a p-chanThe problem is
nel metal-oxide-semiconductor
exacerbated when the
(pMOS) device has a negative bias
with respect to the source. Most of
Note that the tunneling current emisentire circuit is
the discussion here is concentrated
sion is exponentially dependent on both
operating in a highon the nMOS case, while a similar
the electric field in the dielectric and the
parallel exists for the pMOS case.
barrier height. The temperature depentemperature
The barrier height for the purposes
dence of FN tunneling is too complienvironment.
of FN tunneling is calculated as the
cated to be treated in this article and is
difference between the conduction
treated in detail by Pananakakis et al.
band of the dielectric and the Fermi
[7]. To the first order, the FN current
level of the semiconductor. In the
can be assumed to be proportional to
worst case scenario for an nMOSFET, the Fermi level may
the square of the temperature.
be assumed to lie at the conduction band edge, which corresponds to a very strong inversion case or when a highly
Metal-Oxide-Semiconductor in On-State Bias
doped n-type SiC is used. For this condition, the barrier
On-state or forward bias is defined to be when an n-chanheight for FN tunneling is the conduction band offset (elecnel metal-oxide-semiconductor (nMOS) device has a positron affinity difference) between SiC and the dielectric. The
following discussion will assume silicon dioxide (SiO2) as
the dielectric. FN tunneling currents are expected to be
0.7 eV
1.1 eV
much higher at a given temperature and electric field for
3.2 eV 2.95 eV 2.7 eV
SiC-based devices than for Si-based devices because the
conduction band offset between SiC and SiO2 is smaller
Si
than that between Si and SiO2. As shown in Figure 1, the
6H-SiC 4H-SiC SiO2
Si3N4
Al2O3
1.1 eV
conduction band offset in the Si-SiO2 interface is 3.2 eV,
2.85 eV 3.2 eV 9 eV
5.3 eV 8.8 eV
but it is only 2.7 eV for 4H-SiC. For a similar FN tunneling
current, this 0.5-eV difference in the band offset will require
4.7 eV
that the electric field in the dielectric for a 4H-SiC/SiO2 sys3.2 eV
tem be reduced by approximately 1.5# as compared with
3.05 eV
an Si-SiO2 system.
2.6 eV
In commercial Si nMOSFETs, the electric field in SiO2 is
0.5 eV
kept below 4-5 MV/cm so that a reasonable ten-year life is
k = 11.7 9.7
9.7
3.9
7.5
9
achieved [8]. Tunneling is the primary device lifetime limitEcr (MV/cm) =
0.3
2-4 2-3 13-15 8-10 11-13
ing factor for Si metal-oxide-semiconductor (MOS)-based
devices and is rated only to a maximum temperature of
fig 1 The relative dielectric constants and critical electric fields of
125 oC. Reducing the electric field in the dielectric to
various semiconductors (Si, 6H-SiC, 4H-SiC) and dielectrics [SiO2,
silicon nitride (Si3N4), and aluminum oxide (Al2O3)]. The conduc3 MV/cm for an SiC nMOS device will limit the maximum
tion and valence band offests of these are also shown with
gate bias to only +15 V for the typical 50-nm gate dielecrespect to SiO2.
tric thickness at room temperature. At higher temperatures, the electric field in the dielectric (and, hence, the
gate bias) must be made even smaller for the SiC MOS
Schottky Metal
reliability to approach that of an Si MOS transistor. Since
+
+
+
+
the valence band offset of 3.05 eV is larger than the conp
p
p
p
duction band offset of 2.7 eV, pMOSFET reliability may be
nhigher than nMOSFET reliability in the on-state of operation. Ironically, the wider bandgap of SiC seems like a liability rather than an asset for high-temperature operation
because its band structure occupies a larger portion of
the SiO2 band structure.
From this discussion, it seems that the gate tunnel+
ing
current of a conventional SiC nMOS device is higher
n
than Si nMOS devices at similar gate electric fields
and temperatures. However, this conclusion is drawn
Backside Metal
from the worst-case scenario of assuming the barrier
fig 2 The JBS diode under on-state operation.
height for the purposes of FN tunneling is equal to the
A\

IEEE PowEr ElEctronIcs MagazInE

z March 2015

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - March 2015