IEEE Power Electronics Magazine - March 2021 - 57

paper [3]. The intent is to show how regulator's output
impedance can be used to determine phase margin.
Both NISM and in-loop signal injection techniques may
predict the response observed during a large signal steppedor pulsed-load duty. However, there are factors such as
nonlinearity in the power modulator's gain characteristic,
op-amp output slew-rate, integrator windup and amplitude
limiting that may affect the response. There is merit in carrying out large-signal tests on a regulator in order to ensure,
for example, that the compensator has adequate large-signal
handling and gain-bandwidth product for stability.
The time domain testing reported here uses current
pulses that are small in amplitude relative to the base load
current drawn from the regulator. Typically, the pulse
amplitude used in what follows is 10-15% of the base load.
The small, fast excursions of the load current in the time
domain provide consistency in comparisons with smallsignal frequency domain behavior.

5.0 The Loop Gain Paradigm
Figure 2 shows a feedback loop adapted for a loop gain
measurement using signal injection. The excitation source

V _inj(s )

Vref(s) = 0
+

V err(s)

G (s )

V out(s)

FIG 2 Injecting ac small signal voltage into classic feedback loop.

g_PR (s)

LL
ML
FL

r_EQ_OUT (Ω)

def

Va ^ s h
F (4)
vb ^ s h

So loop gain can be determined as the ratio of output
voltage to applied injection voltage.

6.0 Regulators to be Simulated and Tested
The PRM case illustrates how output impedance and loop
gain can be simulated in LTspice. The necessary mapping
for output impedance is illustrated. Real hardware is tested
to yield corresponding metrics in the frequency and time
domains. The time domain response is determined to
observe correspondence across the 2 domains. This material is covered in sub-sections 6.1 through 6.7.
The second example, covered in sub-section 6.8 involving the PI3106, offers no opportunity for simulated or direct
loop gain assessment - It presents a good case for NISM and
time domain response tests on the hardware and outcome
comparisons.

Different power demands can be applied to the regulator
small-signal model shown in the LTspice schematic of Figure 3. The table on the top left corner of the schematic
shows parameters for the PRM power modulator, determined at 3 quiescent operating points. Model figures are
easily derived from the PRM datasheet's power modulator
gain and output resistance characteristics [4]. Resistive

Load Class

ac dec 500 10 10 MEG
.include opamp.sub

55
20
4

1.2
2.2
4

loop gain = G ^ s h . H ^ s h = <

6.1 Simulated NISM Outcome for a PRM

H (s )

Load Class

{V_inj(s)} provides a floating signal relative to the active
power bus. Assuming that the impedance level at Vout at
node {A} is much smaller than on the injector source's negative node {B}, it can be shown that [10]:

Rload (Ω)

LL
ML
FL

41.65
14.5
4.2

PRM_OUT
g_PR
1.2

PR
R_PR
93.3 k

r_EQ_OUT
55

R1
1.5 m

V_inj
AC 0 0

C1
6.2 µ

LOOP_IN

PRM CN (Share) and Output Ports

350 p
U2

20 k

Compensator

inter

External Voltage Sense
and Buffer Stage
sample
U1
R5
1.27 k

C2
I_inj
AC 1 0

8.8 µ
R2
2m

Rload
41.65

Simulation Deck for Remote Sense
R3
500 W PRM.
54.9 k Examination of Zout (ORP) impedance at
output reference plane.
PRM under LL, output setpoint - 48 V dc
with installed ceramics C1 voltage derated
R4
for output setpoint.
1.27 k
No parasitic internal PRM or factorized
bus inductors included.

FIG 3 PRM device model under LL - arranged for output impedance simulation.

March 2021 z IEEE POWER ELECTRONICS MAGAZINE

IEEE Power Electronics Magazine - March 2021

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