IEEE Power Electronics Magazine - March 2021 - 58

of the converter and are not included in simulations. This
assumption is justified later.
The key impedance in Figure 4 used to assess stability is
{Zout(ORP)}, impedance at the output port reference plane.
This consists of the terminating load i.e., {R_load}, parallelled with the capacitor bank and {Zout(PRM)}, the PRM
output impedance. To find {Zout(ORP)}, current source {I_
inj} applies unit amplitude ac current swept over frequency
(see Figure 3). Voltage, determined at the load reference
plane, equates to impedance {Zout(ORP)}.
Simulating the LL condition, the slope of the impedance vs
frequency in Figure 5 is inductive, peaking at 10.94  kHz. The
output impedance is lowered by feedback within the control
loop bandwidth in accordance with equation1, equation2 . With
loop gain dropping with increasing frequency, the less the output impedance is influenced by feedback. Note that the PRM
switches at frequency {Fsw} which varies from part to part from
between 700 kHz and 1.07 MHz. The frequency range beyond
which phase delays start affecting results
due to switching is approximately {Fsw/6} in the band from 117 kHz and 178 kHz. Beyond
Location of Factorized Bus Inductor and Parallel
~ 11 kHz, the loop gain drops away. Beyond
Damping Resistor Branch Omitted in Simulations,
the closed loop bandwidth, {Zout(ORP)} is
Included in the Hardware
dominated instead by the impedance of the
Output
R_load
capacitors in the output filter.
Capacitor Bank
Peaking of group delay of output impedoooo
ance maps to phase margin in a second
order system [2] according to equation 5.
This is plotted in Figure 6.

loadings that match the quiescent operating points are
shown in the top right corner of the figure. These are designated LL (light load which is deemed to be 10% of full load);
an intermediate r.m.s. level - termed ML (median loading or
31.6% of FL) and FL (full or 100% of rated load).
Two ideal sources are shown in Figure 3: these are the
co-located {I_inj} and {V_inj} current and voltage sources.
Only one of these is activated at a time in the forthcoming simulations.
The current injector {I_inj} is used for determining output impedance with {V_inj} nulled. A block diagram of the
modeled setup is shown in Figure 4. Some components in
the evaluation hardware that will be used for comparison
are not included in the simulation: These are the 100 nH factorized bus inductor and 1 X damping resistor, which prevent crosstalk-induced beats when PRMs are paralleled to
synthesize power arrays. They are deemed not to have a significant contribution within the expected loop bandwidth

PRM

Zout (PRM)

Zout (ORP)

(dB)

FIG 4 Output impedances in the regulator system hardware. Device under test is
the PRM.

1 + 1 + 4Q 4
PM ^Q h = arctan
" radians ,
2Q 4
(5)

V (prm_out) = Zout(ORP) (dBΩ)

6
3
0
-3
-6
-9
-12
-15
-18
-21
-24

V (prm_out) Group Delay (s)

1 kHz

10 kHz

10.893167 kHz, 56.166118 µs

FIG 5 Simulated PRM output impedance magnitude (red) and group delay (blue) - LL condition.

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100 kHz

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