IEEE Power Electronics Magazine - March 2023 - 21

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Table 1. Comparison of fabricated 1.2 kV BiDFET with previous BDS implementations.
Switch
Configuration
Diode Bridge + Asymmetric IGBT
5
8.6
Neft & Schauder, IEEE Trans. Ind. Appl., vol. 28, pp. 546-551, 1992
Asymmetric IGBTs + Freewheeling
diodes
Back-to-back symmetric IGBTs
4
Moghe et al., ECCE, pp. 3848-3855, 2012
2
Takei et al., ISPSD, pp. 413-416, 2001
SiC Power MOSFETs + JBS diodes
4
Safari et al., IEEE Trans. Power Electron., vol. 29, no. 5,
pp. 2584-2596, 2014
Back-to-back SiC Power MOSFETs +
antiparallel and series JBS diodes
6
3.1
Ahmed et al., IEEE Trans. Power Electron., vol. 32,
pp. 1232-1244, 2017
Four-terminal SiC Monolithic
BiDFET
1
[1 diode +
1 MOSFET]
1.0
[1 BiDFET]
Low
[2 diodes + 1 IGBT]
5.8
[1 diode + 1 IGBT]
2.2
[1 symmetric +
1 IGBT]
3.1
[1 diode +
1 MOSFET]
Low
Very High
High
Comparison of fabricated 1.2 kV 20 A BiDFET with previous bidirectional switch implementations
Description
Number of components
On-State Voltage
Drop (V)
Switching Loss
High
Low
Gen-1 BiDFeT
The silicon carbide (SiC) BiDirectional FET (BiDFET)
device was proposed [1] and developed to create a single
chip four-terminal bidirectional device with low on-state
drop and switching losses for matrix
converters. A cross-section of the
4-terminal monolithic SiC BiDFET
Gen-1 device is shown in Figure 1. It
contains two adjacent 1.2 kV SiC
JBSFETs integrated in a single chip. A
JBSFET is a MOSFET structure with
an integrated JBS diode to suppress
conduction of the body diode in the
third quadrant.The drain terminals of
JBSFET-1 and JBSFET-2 are internally
connected via the common N+ substrate
and back-side metallization.
These results
demonstrate that the
BiDFET devices can be
paralleled to increase
the power handling
capability.
Each JBSFET cell contains a MOSFET portion integrated
with a JBS diode. The JBSFETs operate with vertical current
flow, like typical high voltage power MOSFETs, ensuring
uniform current distribution within the active area. The
power MOSFET body diode is deactivated using the integrated
JBS diode within each cell to reduce switching losses
and avoid the bipolar degradation phenomenon [2]. The two
JBSFETs provide high voltage blocking capability, low onstate
resistance, excellent FBSOA, and fast switching performance
in each quadrant. High voltage blocking capability
is achieved in both quadrants when the gates G1 and G2 are
shorted to the respective terminals T1
and T2. On-state current flow occurs
in both quadrants with low on-state
resistance when a gate bias (typically
20 V) is applied to both gates G1 and
G2 with respect to terminals T1 and
T2. Power switching is performed in
the first quadrant by toggling gate bias
G1 applied to JBSFET1 with gate G2
held at the on-state gate bias. In the
same manner, power switching is performed
in the third quadrant by toggling
gate bias G2 applied to JBSFET2
with gate G1 held at the on-state gate bias.
The first generation (Gen-1) BiDFET device was designed
using the JBSFET cell cross-section shown in Figure 2(a).
It has a half-cell width of 6.1 µm to accommodate the JBS
diode within the MOSFET cell. The accumulation-mode
channel was chosen to obtain a mobility of 20 cm2/V-s
with a channel length of 0.5 µm to minimize the channel
March 2023 z IEEE POWER ELECTRONICS MAGAZINE 21

IEEE Power Electronics Magazine - March 2023

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