FIG 1 The BiDFET device-Gen 1 implementation. FIG 2 Gen-1 BiDFET device implementation: (a) JBSFET cross-section; (b) BiDFET chip image; (c) custom designed 4-terminal package; (d) encapsulated module. resistance contribution. The devices were fabricated on n-type epitaxial layers with doping concentration of 8 × 1015 cm-3 and 10 µm thickness to achieve a blocking voltage above 1400 V using the hybrid-JTE edge termination [8]. An image of the Gen-1 BiDFET chip is shown in Figure 2(b) with JBSFET1 at the top and JBSFET2 at the bottom. The chip layout contains gate bus bars to distribute the drive voltage with two gate pads per JBSFET for convenient packaging. Since the JBSFET cells have a specific on-resistance 22 IEEE POWER ELECTRONICS MAGAZINE z March 2023 of 11.25 m`Ω-cm2, an active area of 0.45 cm2 was chosen to achieve a total onresistance of 50 m`Ω for the BiDFET. The Gen-1 BiDFET die size is 1.04 cm × 1.10 cm. The devices were fabricated using the NCSU PRESiCE process technology at a commercial foundry X-Fab, TX [9]. The BiDFET process technology is similar to that used for manufacturing SiC power MOSFETs and JBS diodes making these devices commercially viable. After wafer level characterization, the Gen-1 BiDFET dies were mounted in a custom-designed module, as shown in Figure 2(c), with sufficient wire bonds in the active area to reduce the package resistance to less than 1 m`Ω. Figure 2(d) shows the encapsulated 4-terminal module. The measured blocking characteristics for the Gen-1 BiDFET device at 25 oC are shown in Figure 3(a) [3]. The device can support over 1.4 kV in both the first and third quadrants when the gates G1 and G2 are shorted to the respective terminals T1 and T2 as shown in the inset with the device symbol. JBSFET1 supports the voltage in the first quadrant, while JBSFET2 supports the voltage in the