IEEE Power Electronics Magazine - March 2023 - 23

third quadrant. The device exhibits the desired gate voltage
controlled output characteristics with saturated drain
current at lower gate bias voltages (e.g., 5 V) as shown in
Figure 3(b) at 25 oC. The Gen-1 BiDFET has a total onresistance
of 50 m`Ω at a gate bias of 20 V at 25 oC. The
device can handle 20 A at a drain bias of 1 V consistent
with Table 1. The integrated JBS diodes have a voltage
drop of less than 2.5 V to ensure effective bypassing of the
MOSFET body diode [2]. The turn-on, turn-off, and total
switching losses obtained using double pulse testing of
the BiDFET devices [4], performed at a drain supply voltage
of 800 V and current of 10 A, were 620, 300, and 920 µJ.
The total switching loss was observed to decrease with
increasing temperature to 140 oC.
The BiDFET devices can be paralleled to increase the
current handling capability for use in higher power converters.
This was demonstrated by building a half-bridge module
containing two paralleled BiDFET devices in the upper
and lower leg, as shown in Figure 4(a). The encapsulated
module is shown in Figure 4(b). The measured blocking
characteristics for the Gen-1 paralleled BiDFET devices are
shown in Figure 5(a) in both quadrants. The device can support
over 1.4 kV in both the first and third quadrants when
the gates G1 and G2 are shorted to the respective terminals
T1 and T2. The device exhibits the desired gate voltage
controlled output characteristics, as shown in Figure
5(b). It has a total on-resistance of 25 m´Ω at a gate bias of
20 V, which is half that of the single Gen-1 BiDFET chip as
expected. Double pulse testing of the paralleled BiDFET
devices was performed at a
drain supply voltage of 800
V and current of 20 A. The
extracted turn-on, turn-off,
and total switching losses
were 1350, 460, and 1810 µJ,
which are about twice that
of the single Gen-1 BiDFET
chip as expected. These
results demonstrate that
the BiDFET devices can be
paralleled to increase the
power handling capability.
Gen-2 BiDFeT
A significant enhancement
in the BiDFET die performance
has been recently
achieved with an innovative
new chip design and process
technology. The integration
of the JBS diode
inside the MOSFET cell for
the Gen-1 chip design produces
a large cell pitch of
6.1 µm with low channel
density. In order to
simultaneously obtain ohmic contacts to the N+ and P+
regions for the MOSFET while achieving a low leakage current
Schottky contact to the drift region for the JBS diode, it
is necessary to anneal the Nickel contacts at 900 oC [2]. This
process produces an N+ source contact specific resistance
of 0.8 m´Ω-cm2. Modelling of the JBSFET on-resistances has
shown that the total on-resistance is significantly increased
due to the large cell pitch and high source contact resistance
[5].
A much lower specific on-resistance for the MOSFET
cells within the Gen-2 BiDFET device was
achieved by separating the JBS diodes from the MOSFET
cells and locating them at
four corners of the
chip. The MOSFET cell size could then be reduced to
2.8 µm, as shown in Figure 6(a) right side, to achieve
2.2x increase in channel density. The contact to the
P+
region is made orthogonal
to the cross-section to
make the cell pitch smaller. The Nickel contact to
the N+ source region of the MOSFET was annealed at
1000 oC to reduce the specific contact resistance to 0.05
m'Ω-cm2. The specific on-resistance of the fabricated
MOSFET cell with this design and process was measured
to be 4.5 m'Ω-cm2, an improvement by a factor of
2.5-times compared with the Gen-1 devices. In order to
ensure effective bypassing of the MOSFET body-diode,
10% of the active area was ascribed to the JBS diodes
while keeping the die footprint the same as that of the
Gen-1 devices. The Titanium contact to the JBS diodes
was separately fabricated to achieve the Schottky
FIG 3 Gen-1 BiDFET device: (a) blocking characteristics; (b) output characteristics.
FIG 4 Gen-1 BiDFET paralleled device implementation: (a) internal construction; (b) encapsulated
module.
March 2023 z IEEE POWER ELECTRONICS MAGAZINE 23

IEEE Power Electronics Magazine - March 2023

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