IEEE Power Electronics Magazine - March 2023 - 24

due to a slight difference
in the metal texture. The
Gen-2 BiDFET chips were
packaged in the same halfbridge
module designed
for the Gen-1 paralleled
devices as shown in Figure
6(c) and occupy half
the space. The encapsulated
module is shown in
Figure 6(d).
The measured blockFIG
5 Gen-1 BiDFET paralleled devices: (a) blocking characteristics; (b) output characteristics.
ing characteristics for
the Gen-2 BiDFET device
are shown in Figure 7(a)
in
both
quadrants. The
device can support 1.4 kV
in both the first and third
quadrants when the gates
G1 and G2 are shorted to
the respective terminals
T1 and T2. This Gen-2 BiDFET
has
sharper breakdown
characteristics than
the Gen-1 devices.The
device exhibits the desired
gate voltage controlled
output
characteristics
FIG 6 Gen-2 BiDFET device implementation: (a) JBS diode and MOSFET cross-sections; (b)
BiDFET chip image; (c) custom designed 4-terminal package; (d) encapsulated module.
contact. JBS diode test elements with an active area of
0.045 cm2 (the same value as the JBS diodes inside the
JBSFETs in the Gen-2 chip) fabricated with the Gen-2
BiDFETs were found to have an on-state voltage drop
of less than 2.5 V confirming effective bypassing of the
MOSFET body diodes in the BiDFETs. The MOSFET cells
in the remaining 90% of the active area have a calculated
on-resistance of 12 m'Ω for each JBSFET. Consequently,
the new chip architecture and process creates a Gen-2
BiDFET device with an on-resistance of about 25 m'Ω,
which is half that of the Gen-1 device, while maintaining
the same chip size. This is a major technological
improvement for SiC BiDFETs in terms of reducing the
die cost and module size in half. An image of the Gen-2
BiDFET chip is shown in Figure 6(b). The regions with
the JBS diodes in the four corners of the chip are visible
24 IEEE POWER ELECTRONICS MAGAZINE z March 2023
with saturated drain current
at lower gate bias voltages,
as shown in Figure
7(b). It has a total on-resistance
of 27 m'Ω at a gate
bias of 20 V, which is close
to the design value. Double
pulse testing of the Gen-2
BiDFET devices was performed
at a drain supply
voltage of 800 V and current
of 20 A. The extracted
turn-on, turn-off, and total switching losses were 1120,
250, and 1370 µJ. These values are smaller than those
observed for the paralleled Gen-1 BiDFET devices.
A comparison between the Gen-1 BiDFET technology
with the Gen-2 BiDFET technology is provided in
Table 2. The improvements in performance are shown
in the right-hand column. It can be seen that a BiDFET
device on-resistance of 25 mΩ has been achieved with
a remarkable 2-times reduction in SiC chip area, which
is important for the reduction of chip cost and package
size. The capacitances for the single Gen-2 BiDFET
chip are smaller than those measured for the paralleled
Gen-1 BiDFET devices. In particular, the output capacitance
(COSS) for the Gen-2 BiDFET is 1.75 times smaller,
which leads to the reduced switching losses measured
for the Gen-2 BiDFET devices.

IEEE Power Electronics Magazine - March 2023

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