IEEE Power Electronics Magazine - September 2014 - 30
Power Loss (W)
Efficiency (%)
FOM = (QGD + QGS2)*RDSON(pC*X)
replacement for silicon devices in low-voltage POL converter
applications because of their superior on-state and switching
performances. The state-of-the-art enhancement-mode GaN
(eGaN) power transistors have lateral structures with breakdown voltage ratings in the range of 40-200 V [7]. A comparison of switching figures of merit (FOM) for 100-V devices is
shown in Figure 4(a); the eGaN field effect transistors (FETs)
offer nearly a 66% smaller FOM compared to silicon power
transistors with similar ratings. The superior characteristics
enable not only many new applications but also create more
fig 3 Hybrid 1.2-kV/300-A silicon IGBT/SiC SBD and all-SiC MOSstringent requirements for packaging and thermal manageFET/SiC SBD power modules using the SKiM packaging technology.
ment. Figure 4(b) shows the packaging evolution, which
(Image courtesy of Dr. Kevork Haddad, Semikron America.)
clearly suggests that at operating voltages below about
200 V leadless, dual-sidecooled packaging, such
160
as DirectFET, PolarPAK,
and land grid array (LGA)
140
become elegant solutions,
especially for POLs with
QGS2
120
multimegahertz switching
frequencies [8].
100
The challenge is not
QGS2
just
limited to the packag80
ing of discrete chips alone;
the common-source and
60
QGD
QGS2
high-frequency power
QGS2
Q
GD
loop inductances need to
40
be minimized at the conQGD
QGD
QGS2
20
verter level. Thus, the PCB
layout becomes important
QGD
0
to increase the overall
100-V
80-V
80-V
80-V
80-V
power conversion efficieneGaN@FET
MOSFET 1
MOSFET 2
MOSFET 3
MOSFET 4
cy of the POL converter
(a)
and to improve the thermal management [9]. Since
Drain
the chip current ratings of
commercial eGaN FETs
Gate
are typically limited to below 50 A or so, paralleling
Source
of devices to increase the
current ratings presents
SO-8
LFPAK
DirectFET
LGA
additional challenges. Ex90
Device Loss Breakdown
SO-8
perience has shown that
2.5
Package
LFPAK
VIN = 12 V
85
a single high-frequency
DirectFET
Die
VOUT = 1.2 V
2
LGA
loop with paralleled eGaN
80
IOUT = 20 A
FETs results in significant
FS = 1 MHz
82%
1.5
75
efficiency loss and severe
73%
1
chip heating (Figure 5).
70
47%
A
solution to this prob18%
0.5
65
27%
53%
18%
82%
lem is to create separate,
0.5
1
1.5
2
2.5
3
3.5
0
identical parasitic loops
SO-8 LFPAK DirectFET LGA
Switching Frequency (MHz)
with single-chip devices
(b)
and then tie the outputs
with an external bus config 4 (a) The FOM comparison for 80-V devices (VDS = 40 V, I DS = 15 A). (b) The packaging evolution
nection [10]. As shown in
showing a reduction in package parasitic elements [8]. (Images courtesy of Dr. Alexander Lidow, Efficient
Figure 5(a) and (b), this
Power Conversion Corp., United States.)
30
IEEE PowEr ElEctronIcs MagazInE
z September 2014
Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - September 2014
IEEE Power Electronics Magazine - September 2014 - Cover1
IEEE Power Electronics Magazine - September 2014 - Cover2
IEEE Power Electronics Magazine - September 2014 - 1
IEEE Power Electronics Magazine - September 2014 - 2
IEEE Power Electronics Magazine - September 2014 - 3
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