IEEE Power Electronics Magazine - September 2014 - 37

fragmentation of the market has inhibited the adoption of DVS and AVS
The PMBus protocol
and slowed reduction in energy conwas the first time the
sumption by large logic devices. The
AVSBus brings standardization to
commercial power
this energy optimizing process that
supply industry came
will enable wider adoption and greater reduction of energy consumption
together to cooperate
in computing, networking, and teleand create an open
communications equipment.
A power controller may have just
standard.
an AVSBus interface to the logic device being powered, a PMBus interface to a system management controlAVSBus
ler,
or
both.
Having
both
a PMBus and AVSBus interface
The most significant addition in Revision 1.3 was Part III,
provides a number of advantages. For example, the power
the AVSBus specification. In today's systems, every effort is
converter may power up under PMBus control. Once the
being made to reduce the consumption of energy. Today's
voltage to the logic device is present and stable, and the
server power supplies routinely convert worldwide ac
system management controller knows the logic device is
power to a well-regulated 12 Vdc with an efficiency of 94%.
functioning properly, control of the voltage can be transPower supplies with 96-97% efficiency are available in the
ferred from the PMBus to the AVSBus. If there is a fault in
market, but they cost a bit more. Within systems, such as
the power converter, the logic device may not be functionservers, energy-saving policies are being aggressively
ing. The system management controller, however, will get
deployed. For example, a server will turn off a bank of
an alert through the PMBus interface and can take the apmemory or an I/O port controller if it is not being used-
propriate action.
even for a few milliseconds.
Processors, large ASICs and FPGAs can optimize performance and reduce energy consumption by varying their opAVSBus Design Choices
erating voltage, a technique called dynamic voltage scaling
The first draft of the AVSBus standard was brought to the
(DVS). Reducing the supply voltage reduces the energy lost
PMBus specification working group by Travis Summerlin
through the charging and discharging of the metal-oxide-
and Juan Arango of TI. TI had developed a bus and protocol
semiconductor field-effect transistors in a complementary
they thought would be good for the DVS and AVS application
metal-oxide-semiconductor device. As the energy stored in
and offered it to the SMIF. Still, the PMBus specification
a capacitor is proportional to the square of the voltage, even
working group had a number of decisions to make before
a 10% reduction in voltage yields about a 20% reduction in
the specification could be publicly released.
power consumption. Further efficiency gains can be made
The first decision was, how fast? The speed of the bus is
by slowing the logic clock frequency. Another advantage of a
essential to achieve real energy savings. Suppose a procesreduced supply voltage is a reduction in loss due to leakage
sor were to send a command via the PMBus to lower its supcurrent in the logic transistors.
ply voltage. Even at the newly available 1-MHz clock speed, it
Manufacturers of logic devices can take this one step furwould take almost 50 ns just to send the message. The power
ther. Using information, such as gate delay versus operating
supply's PMBus interface would need to receive and process
voltage, obtained during device testing, a device can adjust
the message and drive the power supply's controller to a lowits supply voltage so that it operates at the minimum voltage,
er duty cycle. For a processor that runs at several gigahertz,
and, thus, the minimum energy consumption, for the desired
50 ns is a long time. With the AVSBus running at a speed of,
clock frequency. Going even further, a device can measure
say, 25 MHz, the message is sent in only 1.28 ns. This 40#
its own delay times and adjust the supply voltage to the
improvement in communication delay comes from both the
minimum that assures proper operation at the desired clock
higher clock speed and a smaller, more efficient packet. That
frequency. The logic device can then safely choose the minireduction in delay time results in real energy savings in the
mum clock frequency needed at the time. If an adjustment
processor, as shown in Figure 2.
to the supply voltage is needed, the performance monitoring
In the other direction, when the processor needs its voltfunction in the IC can send a message to its power supply
age to be increased, the speed of the AVSBus is also importo make the necessary change. This closed-loop control of
tant. If the command was sent by the PMBus, it would more
supply voltage as a function of the device's operation is often
than 50 ns before the power supply output voltage began to
called adaptive voltage scaling (AVS).
change. In this interval, the processor must keep its clock
There have been proprietary-, manufacturer-, and prospeed low, which reduces the computing performance.
cessor-specific solutions that allow a processor to control
With the AVSBus, the delay until the output voltage beings
its power supply via a serial bus for several years. This
to change is 40# shorter, allowing the processor to resume
With the increase in bus speed and
the new ZONE protocols, the PMBus
specification working group decided
that it was time to update the SMBus
specifications. The most recent
version of the SMBus specification,
2.0, had been released in 2000. SMBus
3.0 was created to incorporate the
400-kHz and 1-MHz bus speeds and
the ZONE READ and ZONE WRITE
protocols, and to improve the integration with the PMBus specifications.

September 2014

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