IEEE Power Electronics Magazine - September 2014 - 38

back from the slave, such as
being able to read the actual
1.20 V
Logic Device's
voltage or receive an indicaVoltage
tion of a fault. For this, AVSCommand
0.80 V
Bus provides for an optional
PMBus Communication Delay (c50 ns)
signal that the slave uses to
1.20 V
Output Voltage
send information to the mas(Command Sent
ter (AVS_SDATA). Whether
Via PMBus)
0.80 V
or not a device will use the
two- or three-wire version of
1.20 V
Output Voltage
This area represents the energy saved
AVSBus is a decision for the
(Command Sent
with the shorter communication delay.
system designer.
Via AVSBus) 0.80 V
The working group also
AVSBus Communication Delay (c1.28 ns)
considered the question of
whether the AVSBus should
fig 2 The energy savings with AVSBus.
be point to point, limited
to connecting the powered
logic device to the controller
in its power source, or a bus
1.20 V
Logic Device's
structure that would support
Voltage
multiple end points. Given
Command
0.80 V
the speed and distance, the
PMBus Communication Delay (c50 ns)
work i ng g roup chose to
1.20 V
Output Voltage
make the AVSBus point to
(Command Sent
point. This is not the severe
Via PMBus)
0.80 V
limitation it appears to be.
1.20 V
A power supply controller
Output Voltage
This area represents the performance
IC with an AVSBus interface
(Command Sent
improvement with the shorter communication delay.
may control several power
Via AVSBus) 0.80 V
stages operating in a multiAVSBus Communication Delay (c1.28 ns)
phase configuration, several
power stages with indepenfig 3 The performance improvement with AVSBus.
dent outputs, or a combination of each. The AVSBus
specification
allows
for
a
power
supply controller that
high-speed processing sooner. This can result in a notable
can have up to 15 outputs (or rails). This configuration is
processor performance gain, as shown in Figure 3.
often needed for logic devices that may require one voltThe working group settled on a maximum bus speed of
age for the core logic, another voltage for the high-speed
50 MHz. This bus speed can be implemented well over the
I/O interface, and yet another voltage for the standard I/O
10-20-cm distances needed for the AVSBus. Later, a miniinterface. Figure 4 shows the concept of one AVSBus masmum bus speed of 10 MHz was added to the specification.
ter controlling multiple voltage outputs (rails).
Given the requirement for a bus speed of 50 MHz, the
With the electrical interface defined, the next question
next issue was deciding on an electrical interface. The
is the command language. The function of the AVSBus is
working group did not want to invent a new interface; we
much more limited than the general-purpose PMBus. To
wanted to use something that already existed. We considsimplify the implementation, TI used a fixed 32-bit frame
ered a low-voltage differential signaling interface but, in the
and the working group accepted this structure. The details
end, chose to base the AVSBus electrical characteristics on
of how the various commands, including a checksum, fit in
the serial peripheral interface (SPI). The SPI interface is
this 32-bit frame are beyond the scope of this article-but
commonly available, well understood, and low cost. It can
the implementation is both clever and elegant. In addition,
also operate at 50 MHz over the required distance.
if the three-wire AVSBus is used, the bus operation can be
With the electrical interface defined similar to SPI, the
full duplex. That is, if the master is transmitting more than
signal lines are determined. The AVSBus clock signal is
one frame, the slave can start sending responses after it recalled AVS_MCLOCK and is always driven by the bus masceives the first frame. As long as the master keeps transmitter. There is a required signal line for carrying data from the
ting, so can the slave. This doubles the throughput of the
master to the slave called AVS_MDATA. These two signals
bus and shortens the time it may take for the master to get
are all that is needed to implement the AVSBus. However,
status from the slave device.
this does not allow the master to have any information

IEEE PowEr ElEctronIcs MagazInE

z September 2014

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