IEEE Power Electronics Magazine - September 2015 - 39

grid-tied voltage is 3.24-kV line-to-line rms. The DABC
turns off the DAB's LV-side converters so that it runs in
LV side is regulated at 420 V. Figures 13 and 14 show
open-loop dc-dc mode to safely discharge the MV DABthe AFEC and DABC waveforms, respectively, under the
side dc bus voltage. The MV DABC generated fault signal
integration mode. These waveforms also indicate that
turns off the AFEC so that it does not see a load rejection
the interaction between the AFEC and DABC is stable.
since it is operated as a boost converter system. Also,
faults on the LV inverters are communicated to the DABC and AFEC converters.
21 Acquisitions
27 12 October 18:30:55
Tek Stopped
The layout of the converters and the wiring system has been designed carefully to
avoid noise-pick-up loops. All control
VConv
feedback wires and gate power-supply
wires are shielded and grounded.
3
The stability of the closed-loop controlled systems in cascade, such as in the
TIPS system, is very critical. Three individual subsystems are cascaded to make
the TIPS system, and, therefore, stability
VLoad
at each interface between the subsystems needs to be ensured. A total dc bus
capacitance of 90 nF is considered for
the AFEC. With this relatively small dc
2
bus capacitance and energy storage, the
AFEC may have instability issues when
ILoad
connected to an active load such as the
DABC. For stable operation of any cascaded converter systems, the closed-loop
M 2.0 ms 0.5
Ch 2 50.0 A X
200 ns/pt
Ch 3 500 V
megasamples/second
output impedance of the AFEC should be
Ch 4 500 V
A Ch 1
/13.8 V
lower than the closed-loop input impedance of the next stage DABC for all fre- fig 12 Experimental waveforms of the 1,200-V SiC MOSFET-based converter operatquencies [29]. This will ensure that the ing at 35 kVA. (Line current, I load: 50 A/div; converter line voltage, Vconv: 500 V/div;
two subsystems are totally decoupled load line voltage, Vload: 500 V/div; time: 2 ms/div.)
and the control systems of
the two subsystems do not
interact with each other.
Tek Run
Hi Res
3,887 Acquisitions+ 18 December 2014 22:34:45
Buttons
If either the transferred
FEC
ia [500 V/dev.]
A
power increases or the dc
Ch 4 Position
bus voltage increases, the
-2.48 div
3
modulation index of the
Ch 4 Scale
AFEC is reduced, and the
B
ibFEC [5 kV/dev.]
5.0 kV
output impedance of the
rms (C1) 1.683 A
AFEC increases. Similarly,
1
if the power transferred
rms (C2) 1.545 A
increases, the phase angle
icFEC [10 A/dev.]
C
of DABC increases and its
output impedance reduces.
2
rms (C3) 2.112 A
Therefore, it is necessary to
meet the stability criteria
Grid-Drawn FEC Currents
Max (C1) 4.155 A
VaoFEC [2 A/dev.]
A
throughout the operating
range of dc bus voltage and
Pk-Pk (C4) 6.937 kA
power transferred for the
TIPS system.
Mean (C4) -73.84 V
The TIPS system is run
PWM
Voltage
[5
kHz]
f
in the integrated mode.
The AFEC and DABC are
integrated at 7-kV bus volt- fig 13 The AFEC converter three-phase currents and phase A pole voltage under ac 3.42-kV
age with 8-kW load. The ac grid-tied TIPS system integration mode.
September 2015

z IEEE PowEr ElEctronIcs MagazInE

Table of Contents for the Digital Edition of IEEE Power Electronics Magazine - September 2015