Normally, the presence of stray inductance in the gatesource path leads to voltage overshoots in the gate voltage. This leads to undesirable ringing in the gate-source supply VCC1 CM Circuit (icm) Ciso Rectifier Diode Array Transformer Driver Signal Control Signal Isolator and also might cause voltage overshoot on the gate, which might damage the gate isolation. Special care must be taken when designing the gate-source path. The length of this path is kept as short as possible, and parallel traces for the gate and source are provided to minimize this inductance. The printed circuit board (PCB) layout of the gate driver channel is dc-dc shown in Figure 4. In this design, the stray Converter inductance of the gate-source loop is estidc+ mated to be approximately 7.5 nH. High-dv/dt Source Layout Design Considerations Gate Driver Ciso,of Ground VCC2 Ground dc- FIG 3 The CM current path of the high-side gate driver in a half-bridge configuration in the designed gate driver. Short Circuit Protection The HPCL-316J gate driver integrated circuit (IC) used in this design has an inherent short circuit protection scheme. Although the gate driver IC is typically used for Si IGBTs, the protection feature is adapted for SiC MOSFETs by suitably choosing the blanking capacitor (C blank). Figure 5(a) shows the short circuit scheme used in this gate driver. A zener diode (Z 1) Ch1: 250 V/div Ch1: 250 V/div Ch2: 250 V/div Ch2: 250 V/div 320 mA Ch4: 200 mA /div Ch3: 200 mA /div 180 mA Peak Current: 280 mA Ch3: 200 mA /div Time: 100 ns/div Time: 100 ns/div (a) (b) Ch1: 250 V/div Ch1: 250 V/div Ch2: 250 V/div Ch2: 250 V/div 210 mA Ch4: 200 mA /div Ch3: 200 mA /div Ch3: 200 mA /div Peak Current: 200 mA Time: 100 ns/div (c) 90 mA Time: 100 ns/div (d) FIG 4 The CM current from (a) a single source and (b) separate sources during turn on of the device. The CM current from (c) a single source and (d) separate sources during turn off of the device. Ch1: dc-link voltage; Ch2: device voltage; Ch3: the total CM current for (a) and (c) and the CM current through the optoisolator for (b) and (d); Ch4: CM current through the power supply for (b) and (d) [14]. 22 IEEE POWER ELECTRONICS MAGAZINE z September 2019