IEEE Power Electronics Magazine - September 2020 - 30

is a threatening long-term issue for SiC MOSFETs, as it
increases both the on-state resistance and the voltage drop
across the diode during current commutation. Thankfully,
today's materials have matured, and the density of preexisting dislocations in production-grade materials has fallen;
nonetheless, there remain differences among SiC vendors.
Figure 3 shows recent research from Ohio State University
[7], in which third-quadrant data was measured on ten (10)
of Microchip's 1200 V SiC MOSFETs and ten parts each from
two other vendors. With pre- and post-stress data overlapping, Microchip's SiC MOSFETs show no body diode degradation following 100 hours of stress at full-rated current.

Avalanche Ruggedness
A relevant test for verifying avalanche ruggedness is
unclamped inductive switching (UIS). In UIS testing, the
MOSFET is in its OFF state when it is suddenly asked to
swallow a power surge. Since the MOS channel is not
enhanced, all current must avalanche in the die's periphery-a much smaller area than, say, a short-circuit test in
which the current is uniformly distributed across the
device's entire active area (in short circuit withstand tests,
the MOSFET is in the ON state).
Even more meaningful as a field ruggedness measure is
submitting the device to repetitive UIS pulses, or (R-UIS) [8]
[9] [10] [11] [12]. Figures 4 and 5 compare the device's parametric stability and oxide integrity before and after 100,000
repetitive pulses at two-thirds rated current (per MILSTD-750). The data shown in Figure 4 indicate excellent
avalanche ruggedness. Figure 4a reveals some oxide damage (due to the high field in the JFET region during UIS),
but the gate leakage current remains below a few nanoamperes. Minor deviations were observed in drain leakage and on-state resistance but are viewed as insignificant
since VBR, Vth, and the body diode's V F were unaffected by
R-UIS. Figure 5 compares pre- and post-R-UIS stress TDDB
measurements on SiC MOSFETs from Microchip and three

VG = - 5 V

With confidence established in the performance and reliability of the SiC MOSFET, next up in the creation of a total system solution (TSS) is an advanced power package. Though
the final integration of a power discrete or module will forever be a task for the end user, it is nonetheless the component supplier's responsibility to innovate and offer lowinductance power packaging so that designers may take full
advantage of SiC's fast switching speeds.
External module connections may appear simple, but
internal layout issues are both sophisticated and crucial for
system performance. Due to their comparatively small die
size, many SiC MOSFET die must be paralleled to achieve
low on-state resistances for the module. All die must switch
with nearly identical timing and uniform current sharing,
so die interconnection schemes must balance priorities
of symmetry and low inductance. In response to these
requirements, the company has released the SP6LI power
module package format, which inserts only 2.9 nH of stray
inductance into the power loop. For comparison, the parasitic inductance of standard module packages is around
20 nH. Optimal timing and current sharing are achieved
in the SP6LI package with independent series gate resistor slots for each of the twelve available die spaces in the
high and low side switch positions. These independent gate
resistance paths also minimize the inductance inserted into
the gate-source loop, which is known to increase switching
losses and make the system vulnerable to shoot-through.
To minimize power loop inductance, internal dc link connections are made using bus bars arranged in strip lines.
Substrate connections are symmetrically distributed and
as close as possible to the semiconductor die.
The company offers a family of half-bridge products
in the SP6LI at 700 V, 1200 V, and 1700 V classes with

0
VG = - 5 V

-1
ID (A)

-2
-3
-4

-4

-3
-2
VDS (V)

-1

-5
-5

-2
-3
-4

-4

(a)
Pre Stress

VG = - 5 V

-1
ID (A)

Advanced Packaging Technology

-5
-5

other vendors. The gate oxide from Microchip exhibits the
best long-term reliability in this study.

-3
-2
VDS (V)

-1

(b)
Post Stress 10 A After 10 h

Post Stress 10 A After 20 h

-5
-5

-4

-3
VDS (V)

-2

-1

FIG 3 Third-quadrant SiC MOSFET data from SiC MOSFETs, illustrating differences in body diode robustness among three leading SiC
MOSFET suppliers. No degradation is observed in Microchip devices, part a. (Source: Microchip Technology; used with permission.)

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IEEE Power Electronics Magazine - September 2020

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