IEEE Power Electronics Magazine - September 2020 - 40

Phase C Phase B
Control
Unit

LVac
Port

LVdc
Port

HVdc
Port

Phase A

HVac Port

FIG 4 Experimental prototype of the megawatt power electronic transformer. (Source: Tsinghua Lab; used with permission.)

As shown in Figure 6, the SST consists of three stages:
1) ac-dc stage, 2) dc-dc stage, and 3) dc-ac stage. It can
maintain a unity power factor on the grid side, ride through
a temporary grid voltage drop, and enable bidirectional
power flow between the grid and load. Coupled with an
energy storage system and photovoltaic arrays, it can be
used as an electric energy router (EER) for renewable
energy integration and local electric power regulation.
In this study, the PAT model is used to model all 16 IGBTs
and 8 SiC MOSFETs. With the PAT model, DSED can provide
detailed predictions of switching transients in system-level
dynamics [7]. Figures 8(a) and 8(b) show the comparisons
between experimental and DSED simulated waveforms of
an IGBT turn-on transient and a SiC MOSFET turn-off transient, respectively. As it is shown, experimental and DSED
simulated waveforms are in excellent agreement. The DSED
B) Simulation of Switching Transients
method, supported by a PAT model, can accurately predict
in a Solid-State Transformer
not only key switching waveforms (switching delay, rising
The second case is a 50-kVA solid-state transformer (SST)
and falling times, and voltage and current spikes), but also
consisting of 24 switching devices (16 IGBTs and 8 SiC
switching losses within 10% relative error.
MOSFETs) and 1 HFT. The schematic is shown in Figure 6,
Accurate simulation of switching transients in such a
and a picture of the hardware is shown in Figure 7.
medium-scale system has been proven
to be very difficult. There are existing
Table I. Efficiency comparisons between DSED and commercial software.
tools capable of simulating devicelevel transients in low-power applicaDSED
Commercial Software
tions. However, they are not suitable
Tested Case
0.2 s dynamic process
0.2 s dynamic process
for high-power medium- and largeSettings
Max step size 1e-3
Max step size 1e-3
scale system-level applications. Since
Absolute tolerance 1e-4
Absolute tolerance 1e-4
all switching devices are modeled as
CPU Time
17.7 s
6 h 12 min 8 s
high-order equivalent circuits or nonlinear differential equations, the scale
Number of Calculated Points
101874
196061
and stiffness of the simulated circuit
Time Per Step
0.000174 s
0.114 s
can be substantially increased, making
Relative Error of Grid-side Current
0.000704%
0.00130%
the simulated system highly sensitive
Relative Error of HVDC voltage
0.0000537%
0.0000286%
to device parameters. The simulation
Relative Error of LVDC HFT Current
0.00465%
0.00842%
cannot converge unless a set of suitable
software and experimental results. Both the high-frequency waveform (the HFT current, 20 kHz) and the gridside low frequency waveforms were obtained with one
simulation run and they are in good agreement with both
the commercial software and experimental results. Note
that the simulation speed is significantly improved. For
a 0.2-second-long process, the simulation was finished
within only 18 seconds on a personal computer, as shown
in Table I. With the same relative error of 0.01% and the
same maximum step size of 1e-3, the DSED is 1000 time
faster than the commercial software (17.7 s vs. 22,328 s).
This breakthrough speed makes it possible to analyze,
design and optimize the megawatt PET at both device and
system levels.

IEEE POWER ELECTRONICS MAGAZINE

z September 2020

IEEE Power Electronics Magazine - September 2020

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