IEEE Power Electronics Magazine - September 2021 - 31

applications, including examining the factors that drive
inductor losses, inductor size, and the design tradeoffs,
including the impact on EMI. For this work, an ultrathin
multilevel converter topology was selected, built,
and tested. The experimental results obtained from
this converter were used to further refine the operating
setting and component selections that resulted in a
peak efficiency exceeding 98%.
Introduction
Consumer device trends over the last few years have
resulted in the reduction of the power supply thickness to
single-digit millimeters. This trend has placed increasing
demands on power supply design where solutions that are
5 mm or thinner are becoming the norm. Such power supplies
still need to deliver as much as 250 W with limited
cooling, thus requiring power supply solutions with very
high efficiency. Conventional silicon semiconductors and
standard magnetics components cannot yield the efficiencies
needed to meet these new challenges-ultra-thin, high
power, and high efficiency.
In this article, various step-down converter topologies
were reviewed. These topologies were analyzed in conjunction
with magnetic components to design a converter with
maximum of 3.5 mm component thickness that operate
with high efficiency eGaN FETs and minimal airflow. The
converter specifications are:
■ Input voltage range = 40 V through 60 V
■ Output voltage = 20 V
■ Output power = 250 W (12.5 A)
■ Airflow < 150 LFM
Topology Review
The obstacle to achieving a thin dc-dc step-down converter
lies primarily with the magnetic comsponents. Magnetics
can either be embedded into the circuit board [1]-[2], or the
operating frequency can be increased to shrink their size
[3]-[4]. Embedding the magnetics into the circuit board
increases design and assembly complexity, while increasing
frequency requires advanced switching techniques to
reduce switching loss, such as ZVS techniques for the buck
converter [3], [5].
The multiphase synchronous buck converter [6]-[7] is
comprised of multiple interleaved synchronous stages with
each using lower current rated inductors that can be made
thinner than a single inductor equivalent. Unfortunately,
this approach does not address loss as it merely becomes
distributed. The volt-second for each inductor remains
unchanged so that the inductance of each inductor needs
to be higher in comparison to a single-phase approach [8].
The hybrid synchronous buck converter combines a
multilevel converter with a synchronous buck converter to
improve efficiency by using lower voltage devices [9]-[10].
However, the effective inductor frequency is the operating
frequency of the converter, thus precluding it from shrinking.
The switched capacitor converter eliminates the inductor,
making it ideal for a thin design. The main drawback
of this converter is the lack of step-down voltage
ratio flexibility making it difficult to design to specific
output voltage that is not a whole number ratio of the input
voltage [11].
The three-level converter can operate with the same
inductor ripple current as a synchronous buck converter
while the FETs switch at lower frequency and with a lower
inductance [12]-[14]. This converter offers the benefits of
reduced switching loss and inductor size, hence lower overall
power system loss. Due to these attributes, an ultra-thin
48 V to 20 V, 250 W capable converter is presented in this
article. This converter was made possible by using eGaN
FETs and a high-performance inductor design to support it.
Topology Details and
Switching Device Selection
eGaN FETs have lower parasitic
capacitances, on-resistance,
and no reverse recovery,
thus greatly reducing
losses in multi-level converters
compared to silicon
MOSFETs, making them
an ideal choice for a threelevel
converter.
Figure 1 shows the threeWIND
TURBINES-©SHUTTERSTOCK.COM/METAMORWORKS, 5G-©SHUTTERSTOCK.COM/THE MASTERPLAN STD
level converter topology
for the power system presented
in this article. In this
design, 40 V rated FETs are
suitable but for additional
robustness, par ticularly
during startup, the uppermost
FET, a 100 V rated FET
September 2021 z IEEE POWER ELECTRONICS MAGAZINE 31
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