IEEE Power Electronics Magazine - September 2023 - 30

high-frequency power demands for the
high-performance processors that
they are inevitably based on. While
traditional multilayer ceramic capacitors
(MLCCs) have fulfilled the
requirements thus far, stricter constraints
on power density are challenging
the continued usage of the existing
model.
As system engineers look to
deliver the promised and expected
performance in smaller form factors,
provision of the most efficient power
de-coupling solution is a critical
design consideration. In this article,
we examine the decoupling requirements
of typical high-performance
systems, consider how factors such
as equivalent series inductance (ESL)
and capacitance density play a key role in improving performance
density. We then further illustrate how Empower
Semiconductor's E-CAPs can effectively address these
challenges.
Introduction
It is currently estimated that over 1 trillion capacitors are
produced every year, of which 800 billion [1] are surface
mount MLCCs also known as " chip " capacitors.
These ubiquitous devices are used to address requirements
across the complete power and voltage range in applications,
including energy storage, filtering, and decoupling
of power rails to filter out unwanted ripple and noise. The
exponential growth in the creation of high-performance
computing led by the rapid advent of artificial intelligence
(AI) and machine learning, has led to what are collectively
termed high-performance compute applications.
The magnitude and frequency of instantaneous power
demands are growing in steps of 100% for subsequent,
placing a unique and challenging stress on power integrity
solutions.
Challenges of Power Delivery for High-Frequency,
High-Performance Applications
When it comes to the latest data-intensive systems built
around high-performance, high-speed processors, and multiple
power domains that operate with fast transients and low
voltages, designers are finding a growing number of challenges
with conventional MLCC technologies.
These processors are increasingly used on highly
dynamic workloads, such as running AI algorithms and
neural network models for machine learning and inference.
For such applications, the peak current swings become
significant, with instantaneous peak processor currents
of 800 A to 1000 A in tens of nanoseconds becoming the
norm. This results in extremely challenging (di/dt) current
transients These high-performance devices usually
30 IEEE POWER ELECTRONICS MAGAZINE z September 2023
The magnitude and
frequency of
instantaneous power
demands are growing
in steps of 100% for
subsequent, placing a
unique and
challenging stress on
power integrity
solutions.
require multiple low voltage (0.4-1.0
Vdc) power rails and tight adherence
to voltage regulation specifications,
typically within ±1.0%.
Board-mounted switching dc-
dc converters offer a viable method
of provisioning high power direct
to computational devices such as
FPGAs, GPUs, and neural network
processors (NPUs).
While the dc-dc converters
mounted on the PCB provide adequate
dc power to these workloads,
their frequency of operation, and
hence bandwidth (which is the ability
to respond to ultra-fast current transients),
is orders of magnitude lower
than what
is required. Further,
the
sheer volume of such solutions render
them being located at distances far enough away that any
ability to service fast transients is rendered useless by the
high impedance to the processor.
The electrical noise generated from transients, power
supply ripple, and other noise artifacts can significantly
impact the performance of the computational ICs and the
other circuit functions. Signal integrity is tightly associated
with power integrity in any complex application, and such
artifacts can create " ringing " oscillations across the whole
system. Digital processors made with the most advanced
process nodes such as 5 nm have extremely tight tolerances
on voltage supply to avoid " brown-out " at the lower end and
" over-voltage " on the upper end.
Analog ICs used in data conversion signal chains are particularly
vulnerable to power delivery network (PDN) noise,
with its power supply rejection ratio as a critical indicator
of susceptibility. As any analog IC's datasheet will highlight,
small variations of supply voltage can upset the function's
operation, for example, the introduction of jitter on clock signals
or the reduction of analog conversion accuracy.
Decoupling Power Rails
As the last section highlights, minimizing transient, ripple,
and noise artifacts from the PDN in high-frequency, highperformance
applications is paramount. Decoupling PDN
noise artifacts is an established engineering principle where
multiple capacitors, typically MLCCs, of different values and
case sizes, are placed across the supply rails. The aim is to
provide a low impedance return path across a wide frequency
range. To provide the most effective noise cancellation,
the capacitors are placed closest to the noise sources
and the power pins of sensitive ICs. Board layout will influence
MLCC placement, a situation exacerbated by larger
processor ICs requiring many tens of capacitors. At higher
switching and computational frequencies, PCB trace parasitics
and the equivalent circuit characteristics of the
MLCCs also become significant.
IEEE Power Electronics Magazine - September 2023

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