Signal Processing - November 2016 - 146

Decimation Filter
Fixed Point
Mixed Without opt
Mixed with opt

35
Output Error %

Decimation Filter + Band-Pass Filter

25
20
15
10

Fixed Point
Mixed Without opt
Mixed with opt

40
Output Error %

30
20
10

5
0

0
6

8
9
Coefficient Bits

0.36

0.28
0.24
0.20
0.16

Fixed Point
Mixed with opt

No. equ. NAND Gate

Energy per Cycle (pJ)

1,000
0.32

900
800
700

Fixed Point
Mixed with opt

600
6

8
9
Coefficient Bits

FIgure 6. A comparison of approaches in terms of quantization error, energy, and hardware complexity.

from postlayout transistor-level (Nanothe output values to aid visualization.
Sim) simulation of the accelerator, and
As seen, fixed-point coefficient reprethe hardware area is represented as the
sentation results in substantial error.
equivalent number of NAND gates for
While floating-point coefficient reprethe implementation (note that the ensentation reduces this, the error is subergy and area of the mixed fixed-/
stantially reduced even further thanks
floating-point representation impleto a optimization.
mentation is the same with and withFigure 6 provides an overall summary,
out a optimization). The presented
showing the output error (due to quantization), computational energy, and hardware
implementation with optimization leads to
area, versus bit level
a substantially lower
for representing h i, for
error than an impleThe energy-precision
mentation based on
the three implementradeoff associated
fixed-point coeffitations. The output
with quantization in a DSP
cient representation,
error corresponds to
system has always been a especially at low bit
the root-mean-square
critical concern
levels. For example,
error of the output
for the decimation
computed with 6-bit
during design.
filter alone, the prequantized filter cosented approach leads to a 37 # error
efficients h i versus double-precision
reduction compared to a conventional
h i, normalized to the root-meanfixed-point implementation at the 6-bit
square value of the output computed
level. When considering cascading of the
with double -pre cision h i . The comdecimation filter and band-pass filter, the
putational energy is the average energy
corresponding error reduction is 28 # .
per inner-product operation determined
146

IEEE Signal Processing Magazine

November 2016

Comparing the energy consumption
and hardware complexity, for the fixedpoint and mixed fixed-/floating-point
implementations, the presented approaches also lead to hardware-resource savings in addition to reducing
errors (note, the computational energy
and hardware area with and without a
optimization are equivalent). As an example, at the 6-bit level, the presented
approach leads to 1.4 # energy savings
and 1.2 # area savings compared to conventional fixed-point implementation.
Indeed, that approach is shown to yield
such advantages in a broad range of system implementations, involving convolution operations for various tasks (e.g.,
[4] presents its use for optimizing the
implementation of a linear classifier).

Summary
The energy-precision tradeoff associated with quantization in a DSP
system has always been a critical concern during design. Considering the

Table of Contents for the Digital Edition of Signal Processing - November 2016