FALL 2015 VOL. 7 * NO. 4 www.ieee.org/sscs-news features 23 32 0.3 Introduction to Digital I/O 0.2 By Tony Chan Carusone Pulse Responses 14 0.4 Equalization for Electrical Links By John F. Bulzacchelli 0 0 0 0 0 -0.1 -0.3 Clocking Wireline Systems -0.4 By Bryan Casper 0 2 4 6 Time (UI) 8 10 about this image: Historical Trends in Wireline Communications 47 Evolution of Wireline Transceiver Standards 63 0 0 -0.2 42 53 1 0.1 By Behzad Razavi By Ken Chang, Geoff Zhang, and Christopher Borrelli Find out about these overlapping pulse responses in "Introduction to Digital I/O." 75 Looking to the Future A Technical Foundation for RF CMOS Power Amplifiers By Earl McCune By Hirotaka Tamura 83 Three-Dimensional Integration By Subramanian S. Iyer and Toshiaki Kirihata Minimum Power in Analog Amplifying Blocks By Willy Sansen columns/departments 3 4 5 6 7 9 contributors EDitor's notE PrEsiDEnt's cornEr AssociAtE EDitor's ViEW circuit intuitions 90 91 98 108 111 PEoPlE confErEncE rEPorts chAPtErs iEEE nEWs confErEncE cAlEnDAr A circuit for All sEAsons Digital Object Identifier 10.1109/MSSC.2015.2474256 IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 15 1http://www.ieee.org/sscs-news