IEEE Solid-State Circuits Magazine - Fall 2015 - 11
this property at the two extremes:
at very low frequencies, L 1 and L 2
short R T to the input, and at high frequencies, C B does the same. It can be
proved that Z in = R T at all frequencies if L 1 = L 2 and the pole-zero cancellations leading to (10) also hold.
In other words, the conditions stipulated by (13)-(15) apply here as well.
An intuitive argument can explain
why the T-coil network cannot have
zeros in this case. If the circuit does
contain a zero, then Z in must still be
equal to the termination resistance at
the zero frequency, s z . Now suppose
we drive the circuit of Figure 3(c)
with an input of the form exp (s z t),
obtaining Vout = 0. Thus, C L can be
removed. In other words, at s = s z,
the drain load reduces to R D in series with the parallel combination of
C B and L 1 + L 2 + 2M. This combination cannot have a zero impedance
at s ! 0 and hence Z in ! R D .
Output drivers using ESD protection can benefit from T-coils in a
similar manner. Shown in Figure 5,
such an arrangement assumes an
infinite output impedance for the
driver stage and presents a resistance equal to R T to the outside
world. If the output impedance,
R out, is not sufficiently high, a small
resistance, R 2, can be placed in series with L 2 to compensate for its
effect [10], [7]. This resistance is
given by R T / (R out /R T - 1) .
T-Coil Implementation
In the special case where L 1 = L 2, the
inductors lend themselves to a simple
implementation in the form of a symmetric spiral [Figure 6(a)] [7]. Here,
the line spacing is chosen to yield
the desired mutual coupling, and
the outer dimension and the number of turns to provide the required
inductance. To include the parasitic
resistances and capacitances of the
spiral in simulations, a distributed
model can be constructed as shown in
Figure 6(b). Note that the interwinding
capacitance is also taken into account.
As a first-order approximation, this
capacitance appears between E and
F and can be subtracted from the
bridge capacitance, C B .
RT
R2
L2
Output Driver
Iout
CESD
Rout
CB
L1
Zout
Figure 5: An output driver using a T-coil.
E
F
E
(a)
F
(b)
Figure 6: (a) The implementation of T-coil and (b) a distributed model for circuit simulations.
VDD
RD
L2
CB
L1
Vout
CL
Series
Peaking
LS
Vin
M1
Series
Peaking
C1 LS
(a)
CESD1
CB
L1
L2
CESD2
Vout
RT
(b)
Figure 7: The use of series peaking and T-coils in (a) a gain stage with a high output capacitance and (b) an input network with high ESD capacitance.
IEEE SOLID-STATE CIRCUITS MAGAZINE
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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015
IEEE Solid-State Circuits Magazine - Fall 2015 - Cover1
IEEE Solid-State Circuits Magazine - Fall 2015 - Cover2
IEEE Solid-State Circuits Magazine - Fall 2015 - 1
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