IEEE Solid-State Circuits Magazine - Fall 2015 - 16

100
2006
2007
Data Rate (Gb/s)

2008
2009
2010

2011
2012
2013
2014
1
160 150 140 130 120 110 100 90 80 70 60 50 40 30 20
Process Node (nm)

Figure 2: Trends in digital I/O publications at the International Solid-State Circuits
Conference demonstrate a clear move toward high I/O data rates in more advanced CMOS
technologies over time.

Power Efficiency (mW/Gb/s)

1000.0

100.0

10.0
d
/20
10x

1.0

0.1

40
20
30
Channel Loss at Nyquist (dB)

Figure 3: The power efficiency for recent digital I/O publications at the ISSCC plotted versus channel loss.

the data. One may communicate
independent data on each wire,
called single-ended signaling, or
one may pair wires and communicate complementary data on each,
known as differential signaling.
In high-performance digital I/O,
it is often necessary to consider the
traveling-wave nature of data along
the interconnect between dies. This
becomes a necessity whenever the
electrical distance between dies is
comparable to a wavelength at the targeted I/O frequencies. For example,
PCIe 4.0 links operate at 16 Gtransfers/second, so an alternating pattern
of binary 1s and 0s results in a 8-GHz
tone that has a free-space wavelength

fa l l 2 0 15

lower than 4 cm and even less over
printed circuit board (PCB) traces. If
no care is taken, reflections of the
signals traveling along the interconnect will impair the signal's integrity.

Z0
+ R =Z
- T
0

Consequently, such links are generally designed for a particular characteristic impedance and terminated at
either end, as in Figure 4, similar to
controlled-impedance coaxial cable
connections for high-frequency signals
between lab equipment. In the case of
digital I/O, 50 Ω is the most popular
characteristic impedance used.
When a link is designed for a 50-Ω
(or similar) characteristic impedance,
a strong incentive arises to use relatively small voltage swings between
logic 1 and 0, thereby reducing the
V 2 /R power dissipation in the termination resistors. Consider a signal
swinging between ground and 1 V
on a doubly-terminated 50-Ω link,
resulting in a 20-mW power dissipation in the termination resistors. A
bus of 50 such links would consume
1 W in the termination resistors
alone! Hence, signal swings of a few
hundreds of millivolts are typical.
When chips' digital I/Os are
directly coupled, a practical challenge is to establish shared reference
and/or common-mode voltage(s)
between them. The challenge is exacerbated when we wish to bias the
circuits at each end differently-for
example, because they may be made
using different fabrication technologies. In such cases, ac coupling
allows for independent biasing at
either end of the link, as illustrated
in Figure 5, and is incorporated into
many relevant standards.
However, the combination of
the ac-coupling capacitor C C and
termination resistors R T forms a
first-order highpass filter between
the communicating chips. This
results in a slow loss of the signals'
low-frequency content: a drifting
signal whenever a long series of

RT = Z0

Z0
Figure 4: In high-performance I/O, the
interconnect length is comparable to a
wavelength at frequencies of interest, so
it is designed to have a real characteristic
impedance Z 0, typically 50 Ω. The link is
then doubly-terminated at the transmitter
and receiver to minimize reflections.

IEEE SOLID-STATE CIRCUITS MAGAZINE

+
- RT = Z0

CC
RT = Z0

Figure 5: To simplify biasing of the link,
ac coupling is common, introducing a baseline wander in the received waveform.

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015