IEEE Solid-State Circuits Magazine - Fall 2015 - 17

consecutive identical binary digits
(CIDs) appears on the line. Called
baseline wander, the effect can be
combatted in several ways.
First, a very large coupling capacitor C C can be used, thereby establishing a very low cutoff frequency
for the resistor-capacitor highpass
filter. For example, ensuring that the
received 16-Gb/s signal decays by
only 10% of its full-scale value in the
presence of 100 consecutive 1s on
the line requires a coupling capacitor C C = 6- 6.25·10 -9 /50X· ln (0.9)@
. 1.2 nF.
Alternatively,
digital
coding
methods can be applied to make
long strings of CIDs impossible or
improbable. Line codes may deterministically operate on the communicated data to absolutely prevent
CIDs beyond some upper limit. For
example, a popular "8b10b" code [1]
converts every 8 payload bits into
10 encoded bits, thereby introducing
a significant 25% overhead onto the
required data rate but in return ensuring no more than five consecutive 1s
or 0s ever arise. Alternatively, the
transmitted pattern may be scrambled by "exclusive OR" operation with
a pseudorandom pattern so that CIDs
will arise only if the payload data
happens to precisely coincide with
the pseudorandom pattern-highly
improbable for long pseudorandom
patterns. Finally, another option to
ensure robust operation is by designing the receiver to detect and cancel
baseline wander explicitly.

Clocking Approaches
An important part of high-performance digital I/O is the clocking circuitry, the design of which depends
on the clocking strategy employed.
■ Syncrhonous
interfaces require
clocks at either end of the link
having precisely the same frequency and phase as the data.
This is generally impractical for

Precise frequency matching between
the transmitter and receiver can be
guaranteed only if both ends are
synchronized to a common reference. A typical example is illustrated
in Figure 6(a), where the transmitter
generates a clock from a crystal reference and forwards it to the receiver.
In such mesochronous links, receiver
circuits phase shift the clock to

When an I/O circuit's power consumption
is dominated by dynamic power dissipation,
we may expect it to scale in proportion
to the data rate (all else being equal).
high-performance I/O, where the
clock's operating wavelength is
comparable to (or greater than) the
physical distance between chips.
■ Mesochronous interfaces rely on
clocks at either end of the link
that are at precisely the same frequency but have different phase
shifts relative to the data.
■ Plesiochronous interface clocks
operate at frequencies that are
nearly, but not precisely, the same
at the transmitter and receiver.
■ Asynchronous links must operate
without any a priori knowledge of
the clock frequency at the receiver.
Most high-performance digital I/O
interfaces may be characterized as
either mesochronous or plesiochronous, and both require resynchronization of the data at the receiver.

compensate for differences in relative
phase between clock and data.
Even when a link is designed for a
single, specific operating frequency but
independent reference clock sources
are used at either end of the link, small
frequency differences will arise due
to manufacturing and environmental
variations, resulting in a plesiochronous link. Typical frequency errors
may be measured in tens to thousands
of parts per million, resulting in relative clock phases that drift over time.
The phase drift may be compensated
at the receiver by dynamically adjusting the local clock phase and/or frequency to match that of the received
data. In such systems, transitions on
the data pattern may be thought of as
carrying an "embedded" clock. An example, illustrated in Figure 6(b), shows

Clocking

CDR
AFE

Clocking

Clocking
AFE

AFE
Serializer

Output
Drivers

Termination
Equaliztion
Amplification
(a)

Serializer Output
Drivers

Termination
Equaliztion
Amplification
(b)

Figure 6: Clocking approaches for digital I/O include (a) clock forwarding, resulting in a meshochronous link and (b) the recovery of an
embedded clock at the receiver based upon plesiochronous timing references.

IEEE SOLID-STATE CIRCUITS MAGAZINE

fa l l 2 0 15

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015