IEEE Solid-State Circuits Magazine - Fall 2015 - 18

Magnitude Response (dB)

0
-5
-10
-15
-20
-25
-30

4
6
Frequency (GHz)

Figure 7: The measured frequency response magnitude of a 50-Ω characteristic impedance
PCB interconnect totaling 86 cm in length including board connectors.

Main
M n
Mai
Sample
Sam
mple
e

0.3

Pos
Po
o tcu
c rso
so
or
Postcursor

Precursor
Pre
P
rre
eccu
cur
urso
u
ssor
or
o

Normalized Pulse Response

0.4

0.2

0.1

Time (UI)
Figure 8: The 10-Gb/s pulse response of the same 50-Ω characteristic impedance PCB
interconnect totaling 86 cm in length including board connectors.

each end of the link employing its own
crystal frequency reference. The subsystem extracting the embedded clock
generally also resynchronizes the data
and is therefore said to be a clock and
data recovery unit.
In fact both mesochronous and plesiochronous links may employ many of
the same clocking circuits since in both
cases the clock phase must be adjusted
periodically to compensate for variations in temperature, operating voltage,
component aging, etc. as they arise.
Readers are encouraged to review the
survey of high-performance digital I/O
clocking circuitry, "Clocking Wireline
Systems" by Bryan Casper, in this issue.

fa l l 2 0 15

Signal Integrity
Bandwidth Limitations
Increasing data rates through digital I/O
has, in many applications, run into the
electrical interconnect's bandwidth limitations. For example, Figure 7 shows the
measured frequency response of a 50-Ω
characteristic impedance PCB interconnect totaling 86 cm in length including board connectors. Consider digital
I/O using the channel to communicate
data at 10 Gb/s. In the case of an alternating pattern 101010..., the transmit
waveform would principally comprise
a tone at 5 GHz, which would experience 19-dB attenuation. By comparison,

IEEE SOLID-STATE CIRCUITS MAGAZINE

the pattern 1111000011110000... comprises energy principally at 1.25 GHz,
experiencing only 8-dB attenuation.
The differing attenuation experienced by different spectral components of random data degrade the
link's signal integrity.
A time-domain interpretation is
perhaps a better illustration of the impact of bandwidth limitations on link
signal integrity. The interconnect's
finite bandwidth limits rise and fall
times on the binary voltage pattern,
which thereby causes overlap between
the channel's response to neighboring
bits. Consider the received waveform
in response to a single 1 transmitted in
a sea of 0s. Called the channel's pulse
response, the waveform typically exhibits a high peak corresponding to the
binary 1, with energy spread on either
side in time due to the interconnect's
bandwidth limitations. The pulse response of the same PCB interconnect
at 10 Gb/s is plotted in Figure 8, with
symbols highlighting samples of the
pulse response taken one bit time,
or unit interval (UI), apart. The main
sample corresponds to the pulse response's high peak with pre-cursor and
post-cursor samples preceding the following and main sample, respectively.
Overlapping portions of a pulse response from neighboring bits are referred to as intersymbol interference
(ISI). A received waveform is formed
by superimposing, in time, the pulse
responses of each bit in the sequence,
as illustrated in Figure 9, assuming
symmetric positive and negative pulses are transmitted for 1s and 0s. ISI
terms can destructively interfere and
reduce the signal amplitude of any individual bit. When the absolute amplitude of all pre- and post-cursors taken
together exceed the main cursor, they
can (for certain data patterns) overcome the main cursor, causing a logic
1 to be mistaken for a 0.
Though not, strictly speaking, a
bandwidth limitation, crosstalk between neighboring digital I/O links
can also restrict their maximum data
rates. Crosstalk arises due to the
electromagnetic coupling of closely-spaced PCB traces, connectors, or

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015